AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Updated
Jun 7, 2024 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Simple single-port AXI memory interface
Repository gathering basic modules for CDC purpose
An open source, parameterized SystemVerilog digital hardware IP library
Benchmark fo state-of-the-art Precision Scalable MAC Arrays (PSMAs)
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor
SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip
"Mastering SystemVerilog: From Fundamentals to Advanced Programming Techniques"
SystemVerilog Logger
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
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