A FPGA friendly 32 bit RISC-V CPU implementation

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

A 8-bit computer made of 74xx series logic gates and memory ICs.

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

CPU assembly examples

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

合肥工业大学2020年《系统硬件综合设计》（《计算机组成原理》课程设计，CPU）的代码与报告；使用Verilog实现全冒险处理机制的MIPS五段流水CPU，支持MIPS-C3的50条指令。

👾 8086 Microprocessor simulations with Proteus

Logisim实现的五级流水线MIPS CPU

Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree 💾

2020年北航计组课设代码 This is the BUAA Computer Orgnization code project files.

「💻」Simple kernel made in 16-bit assembly only

[2022] From NAND gate to CPU, Compiler, OS, and finally Tetris Game

A ZX Spectrum test for detecting the Z80 CPU type based on the behavior of the CCF/SCF instructions

16-bit machine on Logisim

SoC design targeted at the IceBreaker board

Our final big homework, 32-bit CPU(microprogram) in Proteus.

SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU

《数字设计和计算机体系结构（原书第2版）》第7章的实现

A completely self designed (game) computer, implemented in hardware using an FPGA. Basically every component is self designed, from the ISA up to the PCB and software. Project exists to learn more about the fundamentals of computers and to improve my Verilog skills