"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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Updated
Jul 9, 2023 - Verilog
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
This repository contains projects developed by students of the Bachelor of Computer Engineering program at Qazvin Islamic Azad University (QIAU). The projects cover various topics in computer engineering, including digital systems, microprocessor, logical circuits, computer graphics, and etc.
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>
All my projects, homework, hand writings, course slides and anything I have learned and done during my study in IUT university😊. feel free to give it a ⭐=)
Digital Logic Design (DLD) is a fundamental subject for the engineering students worldwide. Well, many students find it difficult to design the digital circuits properly while pursuing the DLD course in colleges or universities. Therefore, I will try to assist those students by sharing my lab works with them.
Advanced Pheripheral Bus design using verilog HDL
Digital System Design Course (1st year, 2nd Semester)
Arithmetic Unit, Arithmetic Logic Unit and Data Transferring using Tri-state Buffer register have been implemented using flip-flops and gates in Logisim.
Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA
Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications
This is a simple project that shows how to multiply two 8x8 matrixes in Verilog.
verilog model of a 32 bit RISC-V processor core supporting the RV32I instruction set
Contains my resume
Academic Lab Course of the 27th batch of Computer Science & Engineering | University of Rajshahi - 🇧🇩
Implementation and verification of a hardware-based controller for a three-phase induction motor on an FPGA — Bachelor's Thesis [UPC-TTU, 2019]
Developed a Fake Currency Detector using Verilog HDL and Implemented the same on a Basys 3 FPGA Board
Descrições em VHDL desenvolvidas durante Sistemas Digitais 1
My activity in digital systems
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