Digital systems class at uni
Implementation of a low-pass FIR filter in Verilog HDL.
This repository contains projects developed by students of the Bachelor of Computer Engineering program at Qazvin Islamic Azad University (QIAU). The projects cover various topics in computer engineering, including digital systems, microprocessor, logical circuits, computer graphics, and etc..
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>
Cache Controller Project for COE758 Digital Systems Engineering.
Repository focused on giving a complete introductory course to digital systems, applied to robotics and automation.
Seven instructions digital processor for general purpose.
My Verilog Codes for Digital Systems Design Course
My interests and some collaborations
👾 My studies with Verilog and notions of digital systems.
DSDS (Digital system design and synthesis) Lab and class programs of 2021 - 25 batch.
Digital Systems Design, Sharif University of Technology Fall 2022, Instructor: Dr. Amin Foshati
Digital Systems Design Lab, Sharif University of Technology Fall 2022
Simulate a statement through Moore FSM, With a full explanation. This project was my last additional course project for Verilog in Digital Systems Design during my BS in Computer Engineering
Add a description, image, and links to the digital-systems-design topic page so that developers can more easily learn about it.
To associate your repository with the digital-systems-design topic, visit your repo's landing page and select "manage topics."