VeeR EH1 core
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Updated
May 29, 2023 - SystemVerilog
VeeR EH1 core
VeeR EL2 Core
Just a set of Dockerfiles and tools for FuseSoC
A quick SPI BFM to assist in SPI device testing and development
Find first set operation in Verilog-2001 with logarithmic complexity.
A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.
Yet another attempt at bazel rules for fusesoc. This one relies on a hermetic installation of fusesoc and edalize, and not a containerized build. See https://github.com/filmil/bazel_rules_fusesoc for that other bit.
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