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hdl

Here are 78 public repositories matching this topic...

sv-tests

chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

rtl verilog systemverilog hdl compliance-testing symbiflow

Updated Nov 2, 2024
SystemVerilog

tymonx / logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

BrianHGinc / BrianHG-DDR3-Controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

fpga intel verilog xilinx altera systemverilog lattice hdl testbenches ddr3

Updated Apr 8, 2024
SystemVerilog

tymonx / virtio

Virtio implementation in SystemVerilog

cmake fpga model rtl verilog xilinx vivado systemverilog systemc hdl virtio verilator quartus

Updated Jan 23, 2018
SystemVerilog

shehanmunasinghe / tinyGPU

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

gpu simd systemverilog hdl computer-organization processor-design

Updated Jul 14, 2021
SystemVerilog

adamchristiansen / fpga-ethernet-udp

An HDL design for sending data over Ethernet

mac fpga udp ipv4 ip ethernet hdl mii phy

Updated May 8, 2023
SystemVerilog

snbk001 / 100DaysofRTL

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

makefile verilog synthesis systemverilog hdl testbench systemverilog-hdl systemverilog-simulation rtl-design systemverilog-test-bench edge-detector-with-mealy

Updated Nov 6, 2022
SystemVerilog

bensampson5 / libsv

An open source, parameterized SystemVerilog digital hardware IP library

asic fpga hardware ip verilog systemverilog hardware-designs hardware-libraries hdl digital-design asic-library fpga-library

Updated May 26, 2024
SystemVerilog

dpretet / svlogger

SystemVerilog Logger

asic fpga simulation logger logging class verilog systemverilog hdl icarus

Updated Nov 14, 2022
SystemVerilog

ApogeoRV

GabbedT / ApogeoRV

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

asic cpu fpga systemverilog hdl rv32i rv32c rv32m rv32b rv32zfinx

Updated Nov 2, 2024
SystemVerilog

WbXbc

hotwolf / WbXbc

HDL components to build a customized Wishbone crossbar switch

verilog hdl wishbone crossbar

Updated May 30, 2019
SystemVerilog

SkyworksSolutionsInc / fplib

Fixed point math library for SystemVerilog

verilog systemverilog hdl fixedpoint fixed-point-arithmetic

Updated Oct 18, 2024
SystemVerilog

go.debug

semify-eda / go.debug

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

verification eda verilog systemverilog hdl uvm testbench verilator

Updated Oct 14, 2021
SystemVerilog

rubinsteina13 / SV_I2S_RX_CORE

Synthesizable SystemVerilog IP-Core of the I2S Receiver

fpga verilog systemverilog hdl system-verilog cpld i2s i2s-dac ip-core asic-design

Updated Jun 7, 2020
SystemVerilog

BrianHGinc / SystemVerilog-HDMI-encoder-serializer-PLL-generator

SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 through Quartus Prime 20.1.

intel altera hdmi systemverilog dvi hdl quartus hdmi-encoder dvi-encoder

Updated Sep 5, 2021
SystemVerilog

zhang-stephen / ethernet_w5300

Wiznet w5300 driver code, powered by SystemVerilog

socket fpga tcp systemverilog hdl wiznet

Updated Aug 20, 2023
SystemVerilog

takah29 / arm-cpu

Armv5 single-cycle processor

arm cpu verilog systemverilog hdl arm-cpu armv5 armv4

Updated May 21, 2021
SystemVerilog

AkshayXPatil / Design-verification

UVM and Systemverilog based test benches for functional verification of a RAM module

verification systemverilog hdl uvm

Updated Jan 2, 2019
SystemVerilog

Amirarsalan-sn / RISCV-multi-cycle-processor

A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL

cpu hardware risc hdl modelsim system-verilog risc-v quartus multi-cycle-processor

Updated Jun 5, 2023
SystemVerilog

meiniKi / logIP

Logic Analyzer IP Core

asic fpga digital amd ip verilog xilinx vivado ols systemverilog measurements hdl formal-verification basys3 hardware-description-language logicanalyzer sump logip symbiyosys

Updated Jul 23, 2022
SystemVerilog

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