hdl
Here are 167 public repositories matching this topic...
A go-to repository for exploring, learning, and mastering RTL design and verification.
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Jun 21, 2024 - Verilog
HDL libraries and projects
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Jun 21, 2024 - Verilog
Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
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Jun 3, 2024 - Verilog
FPGA-based QOI image compressor and decompressor in Verilog language. 基于FPGA的QOI图像压缩器和解压器。
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Jun 3, 2024 - Verilog
This repo contains HDL-bits solutions
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May 13, 2024 - Verilog
Collection of projects for various FPGA development boards
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May 13, 2024 - Verilog
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
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Apr 30, 2024 - Verilog
This project is a fully automated parking control system implemented using an HDL (Hardware Description Language), more specificaly Verilog. The system is designed to efficiently manage access of vehicles, requesting password and controlling the parking gate arm with the help of sensors.
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May 1, 2024 - Verilog
An efficient multi-format low-precision floating-point multiplier
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Apr 4, 2024 - Verilog
A collection of educational and practical Verilog modules for FPGA design, tested on Delite FPGA MAX 10 with Intel Quartus and ModelSim. Includes utilities like Clock Dividers, Debouncers, Decoders, State Machines, and more.
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Mar 4, 2024 - Verilog
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