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hdl

Here are 52 public repositories matching this topic...

slaclab / surf

A huge VHDL library for FPGA development

python asic fpga firmware vhdl hdl

Updated Nov 4, 2024
VHDL

Nuand / bladeRF-wiphy

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

vhdl rtl hdl ofdm bladerf ofdm-wireless-communications 80211 dsss

Updated Apr 15, 2024
VHDL

alialaei1 / HDLab-FPGA-Development-Board

Open source FPGA development platform

training development board fpga electronics vhdl pcb electronic fpga-game hdl pcb-layout fpga-board electronics-engineering vhdl-code vhdl-examples hdlab electronics-projects pcb-design

Updated Jul 31, 2023
VHDL

stnolting / neoTRNG

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

cryptography asic fpga entropy random vhdl chaos rtl rng random-number-generators hdl key-generator trng entropy-source ring-oscillator asic-design neorv32

Updated Oct 26, 2024
VHDL

Paebbels / PicoBlaze-Library

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

fpga hardware simulation vhdl assembler hardware-architectures verilog synthesis hardware-designs hardware-libraries picoblaze-library poc-library picoblaze-devices hdl soc

Updated Dec 24, 2020
VHDL

dbhi / vboard

Virtual development board for HDL design

vhdl verilog hdl ghdl cosim vpi verilator fli vhpidirect

Updated Mar 31, 2023
VHDL

vankxr / icyradio

Over-engineered SDR development board

Updated Nov 1, 2024
VHDL

prateek22sri / XNOR-net-Binary-connect

A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacement of vector-matrix multiplication to “XNOR + Popcount” operation

neural-network vhdl hdl xnor-net binary-connect

Updated Sep 16, 2018
VHDL

robodhruv / digital-design

VHDL Code Dump for Digital Circuits Lab (EE214), Spring 2017

vhdl hdl digital-design quartus

Updated Feb 1, 2018
VHDL

m-kru / fsva

FuseSoc Verification Automation

fpga hdl fusesoc

Updated Jul 21, 2022
VHDL

davidel / pyxhdl

Python Frontend For VHDL And Verilog

python vhdl verilog systemverilog hdl

Updated Nov 1, 2024
VHDL

alina-andreevna / FPGA_tools

Easy tools for all designs

fpga verilog hdl chdl

Updated Jul 23, 2023
VHDL

akaeba / tinyUART

Lightweight UART core in VHDL

asic fpga hardware controller vhdl uart rs232 hdl vhdl-code uart-transmitter uart-vhdl

Updated Jan 14, 2023
VHDL

NickSica / fpga_cores

verilog systemverilog hdl

Updated Jan 24, 2021
VHDL

AmitKharade82 / VHDL

vhdl vivado hdl vlsi

Updated Jun 10, 2021
VHDL

SnrNotHere16 / FPGADivisionFloatingPoint

A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

c sdk fpga zynq verilog xilinx floating-point hdl division xilinx-vivado microblaze zynq-7000 nexys4ddr floating-ip artix-7 floating-point-conversion

Updated Apr 5, 2022
VHDL

NabilChouba / luxAlgoHDL

VHDL implemetation of LUX algorithm

vhdl rtl hdl lux

Updated Mar 11, 2017
VHDL

mariam-elshakafi / SAP1-VHDL

An implementation of a simple processor (SAP1) using VHDL

vhdl hdl sap1 sap1-vhdl

Updated May 3, 2020
VHDL

ven0m-hue / RTL_Playground

Verilog code practice using the Xilinx Vivado design suite

fpga rtl verilog vivado hdl vlsi xillinx

Updated Nov 4, 2021
VHDL

JoseAmador95 / UoS_RSoC

Reconfigurable Systems on Chip Mini Project

fpga xilinx coursework vivado hdl system-on-chip vitis

Updated Sep 17, 2020
VHDL

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