Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
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Updated
Jun 16, 2024 - C
Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
C library for shared memory and messaging using inter processor interrupts.
A Xilinx Vivado project to implement a Microblaze SOC on FPGA to run C applications
Repo documenting steps to run u-boot on Microblaze without PetaLinux wrappers.
codes of my IUT FPGA LAB
Me playing with FPGAs & the Linux kernel
32-bit MIPS processor implementation
μBlaze Architecture Plugin for Binary Ninja
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
Xilinx Microblaze GNU gcc toolchain (including gdb) for Debian Linux with additional fixes and patches
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