🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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Updated
May 28, 2024 - VHDL
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
Implementação VHDL de um processador de ciclo único com suporte a um subconjunto de instruções ARMv8.
A 5-stage pipelined processor with its own ISA and assembler implemented in VHDL. Link to the schematic diagram:
First project to INP - create processor what accepts brainfuck as its instructions
MyRISC is an educational processor based on the MIPS architecture.
A VHDL implementation of a RISC-V model processor
Custom 64-bit pipelined RISC processor
16-bit RISC processor with von Neumann architecture
Implementing a clock using a custom processor and a MIPS-compatible processor
JFEGS: a virtual processor for the DE1-SoC board, designed in VHDL. The processor ships with an application that is able to compute the Fibonacci sequence.
ISA extension of Ibex core for ASCON lightweight cryptography algorithm
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