Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
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Updated
Sep 15, 2023 - Verilog
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
Install Intel FPGA 'Quartus Prime' software on remote servers
Tutorial de instalação do Quartus Prime no Linux
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
A recreation of Williams Defender 1981 arcade game for DE10-Lite FPGA dev board, written in VHDL.
Full tutorial about how to install Quartus Prime software in different systems
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1
A Python-based IP Core Management Infrastructure.
Remote control infrared signal receiver programmed in VHDL for a Terasic DE1-SoC board.
Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs
This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.
This repo contains all the Verilog HDL files that I made during the course.
This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.
Sends data from an ADC to a UART-USB interface
CAD for automatically configuring FPGA "Marsohod"
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