risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
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Test the SPI1 pheriperal and look at the waveforms
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Jul 19, 2020 - C++
This project is a RISC-V simulator implemented in C,C++,Python, designed to execute RISC-V instructions and provide a simulated environment for testing and development of RISC-V programs. It includes support for a subset of the RISC-V instruction set, memory management, and system calls
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Apr 27, 2023 - C++
risc-v toolchain apple sillicon m1
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Dec 11, 2021 - C++
RISC-V Simulator written in C++.
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Apr 15, 2023 - C++
Demonstration of using Visual Studio Code for RISC-V C/C++ embedded development
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Sep 21, 2022 - C++
This is a basic RISC-V assembler built in C++, it is incomplete, but allows for the assembly of most of RISC-Vs basic ISA into hex for simulators. It outputs the hex as plain text, as it's original purpose is to assemble for another projects of mine.
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Dec 20, 2021 - C++