RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 43 public repositories matching this topic...
A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python
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Jul 1, 2022 - Python
TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples
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Nov 1, 2023 - Python
Shakti: development platform for PlatformIO
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May 31, 2022 - Python
Arm AArch64 to RISC-V Transpiler
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Jun 23, 2020 - Python
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
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May 15, 2024 - Python
RISC-V CPU implementation in Amaranth HDL (aka nMigen)
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Apr 3, 2024 - Python
Microprobe: Microbenchmark generation framework
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Mar 26, 2024 - Python
A RISC-V new instruction discovery tool [Work in Progress]
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Dec 8, 2022 - Python
Nuclei: development platform for PlatformIO
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Jan 4, 2024 - Python
SiFive: development platform for PlatformIO
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Jan 5, 2023 - Python
GreenWaves Technologies RISC-V GAP: development platform for PlatformIO
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Aug 8, 2022 - Python
CHIPS Alliance: development platform for PlatformIO
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Jun 29, 2023 - Python
RISC-V processor implemented in Amaranth
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Jan 31, 2022 - Python
RISC-V Assembly Software Assistant
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Nov 14, 2023 - Python
RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
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Apr 29, 2022 - Python