OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Updated
May 23, 2024 - Python
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
WAL enables programmable waveform analysis.
Display Django permissions in a HTML table that is translatable and easily customized.
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
Sphinx Extension which generates various types of diagrams from Verilog code.
hardware library for hwt (= ipcore repo)
Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
Open source RTL simulation acceleration on commodity hardware
Example of Python and PyTest powered workflow for a HDL simulation
An opinionated build environment for EDA projects
A flexible and scalable development platform for modern FPGA projects.
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