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Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
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Dec 11, 2020 - VHDL
Custom 64-bit pipelined RISC processor
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Feb 11, 2023 - VHDL
Dual-core 16-bit RISC processor
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Dec 13, 2021 - VHDL
Implementation of a 2D Convolution Filter using VHDL for FPGAs.
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Aug 21, 2022 - VHDL
Music spectrum analyzer implemented on a 7-series FPGA with novel DSP algorithms written in VHDL to accurately bin piano keys to frequency ranges and display in real-time
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Feb 20, 2022 - VHDL
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
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May 6, 2023 - VHDL
8-bit MISC processor with pipelining
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Dec 13, 2021 - VHDL
My first processor written in HDL language
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Aug 21, 2022 - VHDL
Mandlebrot fractal engine and native HDMI video pipeline designed in VHDL with a focus on timing analysis and resource utilization
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Feb 21, 2022 - VHDL
Accumulator-based 4-bit processor
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Dec 13, 2021 - VHDL
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