Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
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Updated
Oct 30, 2017 - Verilog
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
Simple SDRAM Controller for DE10-Lite.
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
Projects using the Sipeed Tang Primer FPGA development board
This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz.
simple sdram controller
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
SDRAM controller optimized to a memory bandwidth of 316MB/s
🛠 A SDRAM controller in Verilog HDL
SDR SDRAM Controller with Avalon-MM bus; [Bugged, deprecated]
Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.
Basic implementation of SDRAM controller for De0-nano board.
Verilog HDL implementation of SDRAM controller and SDRAM model
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