uart
Here are 25 public repositories matching this topic...
SUSTech 2024 Spring CS202 Course Project RISC-V 5-Stage-Pipeline CPU
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May 23, 2024 - SystemVerilog
UART interface to a block ram in the Tang Nano 9k FPGA. No pin connections needed, just use the USB UART.
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Jan 2, 2023 - SystemVerilog
FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol
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Dec 2, 2021 - SystemVerilog
UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.
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Jun 17, 2022 - SystemVerilog
This is a re-write of my previous trigger project. This time Tang Nano 9k is the target hardware and the USB UART is used to configure and enable triggering.
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Jul 7, 2023 - SystemVerilog
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Dec 11, 2017 - SystemVerilog
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Aug 4, 2023 - SystemVerilog
Alchitry Au FPGA Board Example Project
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Jan 12, 2024 - SystemVerilog
6.111 Final Project: Freeform Production of Gorgeous Audio
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Dec 13, 2019 - SystemVerilog
This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.
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Jun 18, 2024 - SystemVerilog
RISC-V SoC
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Sep 4, 2023 - SystemVerilog
UART Receiver and Transmitter using Terasic DE-10 Standard FPGA
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Aug 4, 2022 - SystemVerilog
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