A go-to repository for exploring, learning, and mastering RTL design and verification.
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Updated
Jul 7, 2024 - Verilog
A go-to repository for exploring, learning, and mastering RTL design and verification.
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
Contains simuations under Digital Electronics domain. HDL, VHDL based simulation results of various digital circuit blocks.
Single-Cycle CPU for Homework of Computer System Design in CUMT
BDD Gherkin implementation in native SystemVerilog, based on UVM.
These are Verilog (HDL) codes.
This repo contains the EEL2020 course project, which was instructed to be made in hindi.
VUnit is a unit testing framework for VHDL/SystemVerilog
A complete open-source design-for-testing (DFT) Solution
Verilog_Compiler is now available in GitHub Marketplace! This tool can quickly compile Verilog code and check for errors, making it an essential tool for developers.
A Control System for Washing Machine in Verilog HDL and DE10 Lite Board
I am trying to develop my skills through daily practice and consistency.
HDL support for VS Code
Multi-cycle RISC-V processor with RV32I[M] implementation, built during a few days off.
Implementing Convolution of two digital functions each is a sequence of 8 samples,each represented in 2’s compliment form using 8 bits to produce the outputs(15 samples in total) using appropriate number of bits in 2’s compliment form using Verilog. Discrete Convolution is commonly used in signal processing and image processing.
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
Verilog HDL implementation of SDRAM controller and SDRAM model
Motion Estimation implementation by using Verilog HDL
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