vhdl-code
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A 4-bit up counter is a digital circuit that increments its output by one with each clock pulse, counting from 0000 to 1111 in binary, and resetting back to 0000 after reaching 1111.
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Feb 29, 2024 - VHDL
Control program for Heating, Ventilation, Air-conditioning and Cooling unit.
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Apr 15, 2023 - VHDL
Material from the course of Design of Digital Systems at ENSEM - Université de Lorraine.
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Sep 17, 2023 - VHDL
Hardware accelerator for Image processing in FPGA
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Oct 3, 2023 - C++
Some of my CAD projects
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Dec 24, 2023 - VHDL
The VHDL code implements a 4x1 multiplexer (MUX), selecting one of four input signals based on the two select lines and producing a single output.
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Feb 28, 2024 - VHDL
The VHDL code implements a 2x4 decoder, converting two input signals into four output signals based on the input combinations.
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Feb 28, 2024 - VHDL
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
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May 24, 2024 - Verilog
A team-project about a fem vending-machine I had in 2nd year of uni
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Feb 12, 2024 - VHDL
Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.
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Oct 6, 2024 - VHDL
Este repositorio es el hogar del curso de Fundamentos de Electrónica de la Universidad Tecnológica de Pereira. Aquí, los estudiantes y profesores pueden colaborar en el desarrollo y mejora continua del curso, compartiendo materiales didácticos, ejercicios prácticos, proyectos y más.
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Sep 8, 2023 - VHDL
A 4-bit Microprocessor that Performs Arithmetic Logic Operations
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Sep 3, 2023 - VHDL
Generates multi channels sounds from primitives
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Sep 9, 2024 - C++
Aplicações de Circuitos Digitais em VHDL
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Aug 16, 2024 - VHDL
VHDL Processor // Se desarrolló un procesador multipropósito capaz de realizar operaciones aritméticas básicas de suma y resta entre dos números de entre 1 y 16 bits leídos de una memoria RWM de 1024 posiciones.
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Aug 22, 2024 - VHDL
Sine, Cosine, Tan, Arc sin, and Arc Cos Calculator using CORDIC Algorithm.
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Aug 26, 2024 - VHDL
Bilgisayar Organizasyonu Verilog Projeleri
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Jan 12, 2018 - Verilog
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