Implementation of a Tensor Processing Unit for embedded systems and the IoT.
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Updated
Jan 5, 2019 - VHDL
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Image Processing Toolbox in Verilog using Basys3 FPGA
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
💰 A simplified version of an FPGA bitcoin miner 💰
Design and Implementation of a Simple-As-Possible 1 (SAP-1) Computer using an FPGA and VHDL.
Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
This repository is a collection of designs invloving FPGAs and AI technologies.
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary to run your own embedded Linux on your ZYBO here.
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