Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

Plugins for Yosys developed as part of the F4PGA project.

Minimal DVI / HDMI Framebuffer

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

building blocks for accelerating ZK proofs over binary fields

Re-coded Xilinx primitives for Verilator use

Open-source CSI-2 receiver for Xilinx UltraScale parts

中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session

Verilog Implementation of Run Length Encoding for RGB Image Compression

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs

FPGA Tetris written in Verilog

verilog modules

Practices related to the fundamental level of the programming language Verilog.

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

way to use xapp1052 with new version of PCIe IP core（AXI bus）

A coocbook of HDL (primarily Verilog) modules

way to use xapp1052 with old version of PCIe IP core

RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.