learning about FPGA
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Updated
May 20, 2024 - SystemVerilog
learning about FPGA
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Notes after working with Zynq platform using vivado and petalinux
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
Hardware-side component of Hastlayer for Xilinx Vitis FPGAs. See https://hastlayer.com for details.
Library containing various VHDL IPs
8-bit multiplier module implemented on SystemVerilog meant for the xc7s50csga324-1 Spartan 7 FPGA
Undergraduate level RISC-V microcontroller
All projects that utilize the Verilog & SystemVerilog HDL's.
Logic Analyzer IP Core
An FPGA implementation of Cummings' Asynchronous FIFO
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol
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