Must-have verilog systemverilog modules
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Updated
May 28, 2024 - Verilog
Must-have verilog systemverilog modules
32-bit Superscalar RISC-V CPU
Bus bridges and other odds and ends
Plugins for Yosys developed as part of the F4PGA project.
Verilog Implementation of an ARM LEGv8 CPU
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
mirror of https://git.elphel.com/Elphel/x393
An efficient implementation of the Viterbi decoding algorithm in Verilog
mirror of https://git.elphel.com/Elphel/eddr3
A place to keep my synthesizable verilog examples.
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
An introduction to integrated circuit design with Verilog and the Papilio Pro development board.
FIR band-pass filter using Verilog HDL.
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