FireSim 1.16.0 Release

Vitis documentation updates, re-work of FireSim driver code, URI support for tarball/xclbins, Various bumps

Added

• Vitis: support different bitstream build strategies by @davidbiancolin in #1270
• vitis: Support frequency settings provided at bitstream build by @davidbiancolin in #1281
• Adding support for Azure CI by @t14916 in #1262
• Add apply method that takes ReferenceTarget parameter in RAMStyleHint by @russell-horvath in #1306
• adding a Plusargs Bridge, with unit tests and TutorialSuite tests by @sifive-benjamin-morse in #1291
• Add CI typechecking by @abejgonzalez in #1325
• Added UART bridge test by @nandor in #1326
• Added SimpleRocketF1Tests by @nandor in #1330
• Add an Assert-mode for TerminationBridge; expand testing by @davidbiancolin in #1324
• Introduced an interface to capture the user-defined logic of a simuation by @nandor in #1328
• Added a test for the BlockDevBridge by @nandor in #1335
• Added a root widget class and a low-overhead RTTI mechanism by @nandor in #1382
• Added a bridge registry to own all bridge instances by @nandor in #1369
• Added a test for memory accesses and LoadMemWidget by @nandor in #1433
• Add scalaFix by @sifive-benjamin-morse in #1393
• Add VCS metasimulation to CI by @abejgonzalez in #1396
• Add CI for Vitis driver outside of FPGA sims by @abejgonzalez in #1414
• Add reports and checkpoints section to vitis readme by @russell-horvath in #1412
• Add option to the F1 driver to load an AGFI by @nandor in #1434
• Add URI support to tarball path and xclbin path by @sifive-benjamin-morse in #1432
• Add ci:persist-prior-workflows tag to allow prior workflow to run until completion by @sifive-benjamin-morse in #1449
• Add uartlog checking to Linux boots in CI by @abejgonzalez in #1454
• Add build_farm_tag field to AWS EC2 build farm recipe by @abejgonzalez in #1457
• Add buildfarmprefix to AWS resource dict by @abejgonzalez in #1462
• Add PyTest docs by @abejgonzalez in #1269
• Put instPath before label in AutoCounter output by @timsnyder-siv in #1274
• Add workshop info to README.md by @sagark in #1411
• Bump to latest rocket-chip/scala2.13 by @jerryz123 in #1392
• Bump SBT to 1.8.2 by @abejgonzalez in #1446
• Support AL2 manager instances by @abejgonzalez in #1460
• AL2 Auto-Setup NICE DCV by @abejgonzalez in #1468
• Expand TracerV to support more than 7 IPC by @sifive-benjamin-morse in #1383

Changed

• Expose frequency in the builddcp script by @russell-horvath in #1229
• Match field order in channel info by @nandor in #1264
• Localize Java temp directory + Revert to using sbt-launch.jar by @abejgonzalez in #1257
• build setup: make env.sh sourcable in contexts without conda functions by @davidbiancolin in #1285
• Relaxed restrictions on pipe channel types by @nandor in #1263
• Move XDC circuit paths to config by @fabianschuiki in #1308
• Moved chipyard tests to main FireSim repository by @nandor in #1314
• Rewrite MIDAS tests by @nandor in #1327
• Eliminate virtual inheritance and simplify tests by @nandor in #1323
• Remove references to buildafi; replace with buildbitstream by @davidbiancolin in #1287
• Move termination to Run Farm Inst + monitor_jobs small rework by @abejgonzalez in #1322
• Provided tests with their own random number generator by @nandor in #1338
• Moved MMIO struct type definitions to headers by @nandor in #1331
• Moved widget logic to individual classes by @nandor in #1339
• Switch VCS simulation over to DPI by @nandor in #1332
• Introduced a uniform harness over bridge tests by @nandor in #1336
• Separated testing from peek-poke logic by @nandor in #1341
• VCS and Verilator DPI switchover by @nandor in #1348
• Improve the names of synchronisation primitives in simif_emul by @nandor in #1364
• Replace AXI4 configuration with structures by @nandor in #1358
• Split TutorialSuite into multiple files and helpers by @nandor in #1355
• Introduced a uniform harness across all simulations by @nandor in #1342
• Moved constructor macros to the constructor header by @nandor in #1359
• Eliminate random number generation from simif by @nandor in #1367
• Split target-agnostic.mk into multiple files by @nandor in #1353
• Stream Engine IO interfaces by @nandor in #1366
• Split timing functions from simif.h by @nandor in #1371
• Split simulation_t from simif.h by @nandor in #1372
• [library] Re-organised library file structure by @nandor in #1361
• Remove the use of DPI utilities from dpi.cc by @nandor in #1379
• Separate XSIM from f1 into simif_xsim by @nandor in #1374
• Split project Makefrag into multiple components by @nandor in #1354
• Cache the classpath between SBT runs by @nandor in #1390
• Enable clang-tidy on C++ sources by @nandor in #1400
• Moved simulation step control to the PeekPoke bridge by @nandor in #1399
• [library] Introduced a unique main to the simulation. by @nandor in #1368
• Passed memory region offsets to genHeader by @nandor in #1416
• Removed the compiler-generated runtime config by @nandor in #1422
• Re-enabled timeout detection for harnesses by @nandor in #1423
• Moved non-host IF functions from simif_t into simulation_t by @nandor in #1424
• Restored the runtime config generation phase by @nandor in #1425
• Remove constructor.h and replace it with a Scala-generated header by @nandor in #1398
• Enabled scalafmt on more sources by @nandor in #1429
• VCS post-synthesis RTL simulators by @nandor in #1438
• Extended tests to work with post-synth RTL by @nandor in #1439
• Converted FASEDMemoryTimingModel into a bridge by @nandor in #1440
• Move bridge init/finish handling into the simulation base by @nandor in #1441
• Removed test_harness_bridge and simplified harnesses by @nandor in #1442
• Bump Conda to 22.11.1-4 by @abejgonzalez in #1481
• New Local FPGA Tutorial by @abejgonzalez in #1453
• FPGA-managed bridge stream support in metasimulation by @davidbiancolin in #1181
• Setup defaults to be single-node by @abejgonzalez in #1260
• Changed "firesim infrasetup" to deploy using a tarball. by @sifive-benjamin-morse in #1299
• Switch to py script for XRT shell flashing by @abejgonzalez in #1385
• Update Vitis docs | Bump FPGA platform to 2022.1 by @abejgonzalez in #1397
• Force using 2022.1 Vitis by @abejgonzalez in #1410
• Localize .ivy2 and .sbt folders to FireSim repo by @abejgonzalez in #1456
• Unpin most conda reqs now that we have a lockfile by @abejgonzalez in #1451

Fixed

• Do not materialize a stream engine if no streams are used by @nandor in #1430
• Do not materialize memory connections if the target does not use them by @nandor in #1431
• Introduced a full verilator/vcs/debug matrix by @nandor in #1435
• Re-enable compilation of the Dromajo bridge by @nandor in #1384
• Bump CI to Ubuntu 20.04 + new checkout action by @abejgonzalez in #1265
• remove unused import RocketTilesKey (copy #1278) by @mergify in #1279
• fix vcs metasims by @sagark in #1280
• aws-fpga: avoid invocations of git clean by @davidbiancolin in #1283
• Fix and Register TargetUtils + Midas Scala Tests in CI by @davidbiancolin in #1284
• manager: fix string interpolation in buildconfigfile by @davidbiancolin in #1288
• Manager: Add back InfoStreamLoggers to buildbitstream related tasks by @davidbiancolin in #1292
• fixed runners for midas / targetutils tests by @t14916 in #1294
• Fix SimUtils tests by @nandor in #1295
• Fix Reset Synchronizer For InitValues == 0 by @davidbiancolin in #1296
• Fix MCRAMs optimization with more strict FPGA backend passes by @russell-horvath in #1298
• Fix C++ compiler warnings by @nandor in #1302
• AutoCounter: Add cinttypes to autocounter.h for format specifier bug by @davidbiancolin in #1304
• Regenerate AGFIs to fix references to removed FXXMHz classes by @davidbiancolin in #1300
• CI Cleanup: Camel-case AWS CI variables by @abejgonzalez in #1321
• CI Cleanup: Fix deprecations + Remove extra whitespace by @abejgonzalez in #1320
• CI Rework: More Aggressive Culling Of FPGA Resources, Slack/PR Notifications by @abejgonzalez in #1316
• Remove raw pointers from bridge port address creation by @nandor in #1309
• Fixed invalid memory access of MMIO port addresses by @nandor in #1317
• Slightly increased timeouts of fpga jobs in CI by @t14916 in #1333
• Fixed firesim.bridges CI tests by @nandor in #1334
• Fix documentation on Vitis deploy manager by @abejgonzalez in #1343
• Fixed GCC/Clang compilation issues by @nandor in #1360
• Fix a memory leak in the serial bridge by @nandor in #1373
• Fix Valgrind false positives by @nandor in #1376
• Fix Assorted Scala warnings by @sifive-benjamin-morse in #1378
• Fixes needed to support Scala 2.13 by @sifive-benjamin-morse in #1388
• Fix metasim due to tarball deployment and add CI by @abejgonzalez in #1387
• Fixed platform configs not being applied by @nandor in #1394
• Fix Vitis CI by @abejgonzalez in #1344
• Fixes for Chisel 3.6 support by @sifive-benjamin-morse in #1395
• Applied clang-tidy fixes by @nandor in #1402
• Fix loadmem bug in firesim_tsi.cc by @jerryz123 in #1401
• Fix incremental builds triggered by scala changes by @nandor in #1408
• Fix Vitis driver compilation + Fix CY-as-top driver builds by @abejgonzalez in #1409
• Fix Vitis driver CI check by @abejgonzalez in #1415
• Fixed missing array include by @nandor in #1417
• bump aws-fpga to remove bloat files in hdk/cl/examples + fix typo by @russell-horvath in #1406
• Fix wiring of unused ports by @nandor in #1437
• Fix replace-rtl ordering problem by @nandor in #1444
• Fix uartlog checking in CI for Linux boot by @abejgonzalez in #1467
• [SimWrapper] Remove unused SimReadyValidRecord; NFC by @fabianschuiki in #1337
• manager: update paramiko date threshold by @davidbiancolin in #1357
• bump aws-fpga w/ Route 35-1 and Synth-8-6340 warning promotion by @russell-horvath in #1391
• Use the new config filename in bitbuilder logging by @caizixian in #1413
• Test for existing TracerV bridge including trigger modes by @sifive-benjamin-morse in #1426
• Update doc of always_expand_run_farm for rename by @timsnyder-siv in #1427
• pickup fab-classic#77 by bumping to 1.19.2 by @timsnyder-siv in #1443
• Dedup. CI Requirements by @abejgonzalez in #1445
• Don't hash dict in CI by @abejgonzalez in #1450
• Revert to UInt64 for offsetConst in SerialBridge by @abejgonzalez in #1463
• Update .gitignore for .ivy2/.sbt by @abejgonzalez in #1465
• Bump Chipyard + Update Vitis Xclbin + AWS AGFIs by @abejgonzalez in #1466
• Bump conda-reqs | Bump Chipyard by @abejgonzalez in #1470
• Use FREQUENCY as a prereq in Vitis builds by @abejgonzalez in #1472
• firesim gemmini tutorial configs by @sagark in #1480
• Fix typos in Vitis docs by @ncppd in #1483