FIRRTL v1.5.6

Feature

• Support 0-bit literals (#2544)

FIRRTL v1.5.5

Feature

• FIRRTL version support (#2543)
• Add Serializer.lazily for buffered serialization (#2554, #2560)

BugFix

• Make the Parser handle errors more gracefully (#2549)

Security

• Bump protobuf runtime to avoid CVE-2021-22569 (#2535)

FIRRTL v1.5.3

Performance

• Use circuit name hashCode for circuit anno hashCode (#2504)

BugFix

• Fix optimization of register with reset but invalid connection (#2520)
• Fix incorrect deprecation warning for TargetDirAnnotation (#2511)
• Make MemConf's MemPort serialization deterministic (#2508)
• Fix anno deserialization when class field is not first (#2501)

FIRRTL v1.5.2

BugFix

• Fix handling of modulus (rem) on SInts (#2485)

FIRRTL v1.5.1

BugFix

• Fix faulty MemorySynthInit behavior (#2468)
  Fix & test MemorySynthInit behavior with MemoryArrayInitAnnotation and MemoryScalarInitAnnotation.
  Add test case for MemoryRandomInitAnnotation which is, on the contrary, expected not to leak any randomization statement in synthesis context.
• Fixed emission-options flags to match their functionality (#2472)
• make PropagatePreset play nice with verification statements (#2453)
  This used to crash, now preset is treated as 0 for verification statements
• [smt] correct comparison for out-of-bounds memory access check (#2463)

FIRRTL v1.5.0

Feature

• Allow Side Effecting Statement to have Names (#2057)
• Stop padding multiply and divide ops (#2058)
• Refactor emitter (#1879)
• Add SortModules Transform (#1905)
• Make {Stage, FirrtlStage}.run protected (#1926)
• Create annotation to allow inline readmem in Verilog (#2107)
• Add -fpga flag to enable FPGA-oriented compilation strategies (currently for memories) (#2111)
• Add NoConstantPropagationAnnotation to disable constant propagation (#2150)
• Add options for memory initialization inside or outside the ifndef SYNTHESIS block. (#2166)
• Add indent parameter to Serializer.serialize() (#2177)
• Rewrite vlsi_mem_gen into a Firrtl Transform, Add GenVerilogMemBehaviorModelAnno & vlsiMemGen (#2202)
• Implement MFC-style source locator compression (#2212)
• Improve performance of RenameMap in LowerTypes (#2233)
• Add -X mhigh compiler for minimal high form (#2268)
• Add Protocol Buffer emission export, this adds infrastructure and annotations that let a user emit a FIRRTL circuit as a Protocol Buffer. (#2271)
• Add a new option to the FIRRTL compiler, "--start-from = ". If used, this will cause the compiler to assume that the input FIRRTL circuit is already in the specific form. It will then skip unnecessary passes given this information. (#2273)
• Relax spec on 0-bit mux select, use SFC behavior, change the FIRRTL specification document to allow for 0-bit mux selects. (#2285)
• Implement NoCommonSubexpressionElimination (#2291)
• Add RTLIL Backend. (#2331)
  Adds code generation backend targeting RTLIL IR for use with the Yosys open synthesis tool.
• Disable random init (#2396)
  optional to remove random initialization code in emitted Verilog.
• Let firrtl based applications run despite loading unknown annotations (#2387)
  Use command-line option --allow-unrecognized-annotations
• Improve ANTLR Parser (#2343)
  It now uses substantially less memory on large designs
• Implement CustomRadixTransform for wave viewers (#2434)
• Enable memory initialization in synthesis for FPGA targets (#2430)
• Add --dont-fold option to disable folding prim ops (#2040)

API Removals

• Memlib Refactor, switch to new API. (#2191)
• Modify and optimize performance of propagate annotations (#2393)
  When a transform deletes an Annotation, a DeletedAnnotation is no longer created. Furthermore, debug-mode logging no longer captures any information about annotation changes between transforms. If any of this behavior is desired, please file an issue to restore it under a debug flag.
• Remove The WriteEmitted Phase (#2390)
• Remove firrtl.ExecutionOptionsManager (#2422)
• Remove firrtl.transforms.BlackBoxSourceHelper.fileListName. (#2426)
• Remove firrtl.transforms.InferResets.DifferingDriverTypesException (#2425)
• Remove firrtl.transforms.InlineAcrossCastsTransform. (#2424)
• Remove firrtl.FIRRTLException (#2421)
• Remove firrtl.Utils.get_flip and firrtl.Utils.indent (#2420)
• Remove trait firrtl.util.BackendCompilationUtilities (#2423)
• Remove firrtl.Driver (#2419)
• Remove Scala 2.11 (#2062)
• Fix RemoveAccesses, delete CSESubAccesses (#2157)

API Deprecations

• Deprecate all mutable methods on RenameMap (#2444)
  For constructing RenameMaps, use firrtl.renamemap.MutableRenameMap.
• Deprecate ToWorkingIR (#2028)
• Deprecate InlineCasts, add InlineAcrossCasts (#2146)
• Deprecate memlib APIs.(#2199)
• Remove java.io in FileUtils, Add deprecation annotation in FileUtils (#2256)
• Deprecate BlackBoxResourceAnno (#2262)

BugFix

• Fix Serializer for single indented DefModule emission (#2332)
• Bug fix for VerilogPrep using wrong type. (#1932)
• Fix dshl zero-width shift behavior (#2339)
• Fix RemoveWires handling of invalidated non-UInt wires (#1949)
• Fix Type Error fuzzer Example code (#1960)
• Fix subaccess (#1984)
• Remove explicit pom scm from build.sbt (#2004)
• ExpandWhens: ensure that statement names are maintained (#2082)
• Fix ProtoBuf conversions for Verification IR (#2100)
• Fix CSESubAccesses for SubAccesses with flips (#2112)
• Fix cat of zero-width SInt (#2116)
• Fix width of constant propagation of SInt with zero (#2120)
• Fix issue where inlined cvt could cause crash (#2124)
• Legalize neg: -x becomes 0 - x (#2128)
• Ensure InlineCasts does not inline complex Expressions (#2130)
• Fix bug in zero-width memory removal (#2153)
• Don't use declaration-assigns for wires representing mem ports (#2189)
• Fix CheckWidths error message for uninferred width (#2196)
• Fix SBT deprecation warnings (#2214)
• Fix renaming of local targets in InlineInstances (#2238)
• WiringTransform: cannot run after RemoveWires (#2240)
• Fix MultiInfo parser + serialization bug (#2265)
• [spec] Explicit widths may be non-negative, not just positive (#2277)
• Dedup attribute annos, restore annotation order when dedupping annotations (#2297)
• Fix Specification Memory Port Types (#2319)
• Fix width of signed addition when input to mux (#2440)
• Support parsing missing keywords as ids (#2381)
• smt: correctly serialize array index on read (#2446)
• BlackBoxSourceHelper: ensure trailing newline in .f file (#2405)
• Hotfix for Vector Reg Init LegalizeConnects Bug (#2380)
• TopWiring: filter out unnamed declarations when building source lists (#2376)
• smt: fix handling of div primitive in formal backend (#2409)
• transforms.formal: ensure named statements as output (#2367)

Dependency Bumping

• Update sbt to 1.5.7 (#2443)
• Update sbt to 1.5.6 (#2441)
• Update os-lib to 0.8.0 (#2442)
• Update sbt-scalafmt to 2.4.5 (#2433)
• Update sbt-scalafix to 0.9.33 (#2431)
• Update sbt-ci-release to 1.5.10 (#2418)
• Update scalacheck-1-14, ... to 3.2.1.0 (#1850)
• Update sbt-ci-release to 1.5.9 (#2364)
• Update scala-parallel-collections to 1.0.4 (#2377)
• Update sbt-mima-plugin to 1.0.1 (#2385)
• Update sbt-protobuf to 0.7.1 (#2378)
• Update sbt-scalafix to 0.9.32 (#2414)
• Update sbt-scalafmt to 2.4.4 (#2417)
• Update commons-text to 1.9 (#1789)
• Update sbt-assembly to 1.1.0 (#1706)
• Update scala-library, scala-reflect to 2.12.15 (#2358)
• Update scala-library, scala-reflect to 2.13.7 (#2401)
• Update sbt-unidoc to 0.5.0 (#2394)
• Update json4s-native to 3.6.12 (#2406)
• Update sbt-scoverage to 1.9.2 (#2402)
• Update antlr4, antlr4-runtime to 4.9.3 (#2407)

Miscellany

• Improve performance of LowerTypes renaming (#2024)
• full64 is required to detect VCS. (#1930)
• Remove caching from RenameMap (#1938)
• Fix Type Error fuzzer Example code (#1960)
• Make MultiTargetAnnotation.targets a def (#1969)
• add weak and strong to Utils.v_keywords (#1983)
• Suport ir.SubAccess in Utils.splitRef (#2021)
• IR: turn some IR nodes into data classes (#2071)
• Emit space after 'if' for all Verilog conditional synchronous assignments (#2091)
• don't use protoc-jar anymore, mill can handle it better. (#2162)
• Constant propagation of the Xor op folds xor(a, SInt(0)) toasUInt(a). For comparison, Or folds to asUInt(pad(a, W)). (#2179)
• Make InferTypes error on enable conditions > 1-bit wide (#2182)
• With Stage/Phase, users can provide complex functionality at the phase level rather than just the transform level. It is useful to have the same logging information at that level. Note that this change still logs transforms in the same way (#2190)
• Make MustDeduplicateAnnotation deletable (#2215)
• This function will safely wrap any unserializeable annotations in UnserializeableAnnotations so that they can be safely serialized to JSON for logging. (#2227)
• Replace mem macros renaming (#2243)
• ir: make HashCode.toHashString public. This will allow chiseltest to save the hash code to disk for the purpose of caching simulation binaries. (#2302)
• add emitter for optimized low firrtl (#2304)
• Require Andr, Orr, Xorr, Neg to have one operand (#2312)
• Uses virtual method .getBytesBuffered: Iterable[Array[Byte]] to optimize file emission. (#2334)
• Multiprotobuf algorithm now pulls the top module from the protobufs (#2344)
• [spec] Fix formatting of example of memory port types. (#2368)
• Have Flatten & InlineInstances remove their annotations (#2374)
• Update spec on extmodule with defname, parameter (#2413)
• smt: ensure that all signals have a unique name (#1943)
• Fix SMT Memory Bug (#1942)
• smt: add support for write-first memories (#1948)
• smt: add support for uninterpreted ext modules (#1994)
• smt: run DeadCodeElimination after PropagatePresetAnnotations (#2036)
• SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)
• SMT Backend: model Invalid and Division by Zero with DefRandom nodes (#2104)
• SMT: memory port inout fields cannot be used as RHS expressions (#2105)
• smt: use existing bitWidth API(#2175)
• make PresetRegAnnotation public (#2254)
• Replace hard coded line separators with system specific ones (#2281)
• PropagatePresetAnnotations: remove false prerequisites (#2323)(#2325)
• smt make SMTLib + Btor2 emitters public objects, This will make it easier for formal verification libraries to make use of these emitters. (#2326)
• treat stop with non-zero ret like an assertion (#2338)

FIRRTL v1.5.0-RC2

1.5.0-RC2 includes all changes from 1.5.0-RC1 so please see the RC1 release notes.

Feature

• Add RTLIL Backend. (#2331)
  Adds code generation backend targeting RTLIL IR for use with the Yosys open synthesis tool.
• Disable random init (#2396)
  optional to remove random initialization code in emitted Verilog.
• Let firrtl based applications run despite loading unknown annotations (#2387)
  Use command-line option --allow-unrecognized-annotations
• Improve ANTLR Parser (#2343)
  It now uses substantially less memory on large designs
• Implement CustomRadixTransform for wave viewers (#2434)
• Enable memory initialization in synthesis for FPGA targets (#2430)

API Removals

• Modify and optimize performance of propagate annotations (#2393)
  When a transform deletes an Annotation, a DeletedAnnotation is no longer created. Furthermore, debug-mode logging no longer captures any information about annotation changes between transforms. If any of this behavior is desired, please file an issue to restore it under a debug flag.
• Remove The WriteEmitted Phase (#2390)
• Remove firrtl.ExecutionOptionsManager (#2422)
• Remove firrtl.transforms.BlackBoxSourceHelper.fileListName. (#2426)
• Remove firrtl.transforms.InferResets.DifferingDriverTypesException (#2425)
• Remove firrtl.transforms.InlineAcrossCastsTransform. (#2424)
• Remove firrtl.FIRRTLException (#2421)
• Remove firrtl.Utils.get_flip and firrtl.Utils.indent (#2420)
• Remove trait firrtl.util.BackendCompilationUtilities (#2423)
• Remove firrtl.Driver (#2419)

API Deprecations

• Deprecate all mutable methods on RenameMap (#2444)
  For constructing RenameMaps, use firrtl.renamemap.MutableRenameMap.

BugFix

• Fix width of signed addition when input to mux (#2440)
• Support parsing missing keywords as ids (#2381)
• smt: correctly serialize array index on read (#2446)
• BlackBoxSourceHelper: ensure trailing newline in .f file (#2405)
• Hotfix for Vector Reg Init LegalizeConnects Bug (#2380)
• TopWiring: filter out unnamed declarations when building source lists (#2376)
• smt: fix handling of div primitive in formal backend (#2409)
• transforms.formal: ensure named statements as output (#2367)

Dependency Bumping

• Update sbt to 1.5.7 (#2443)
• Update sbt to 1.5.6 (#2441)
• Update os-lib to 0.8.0 (#2442)
• Update sbt-scalafmt to 2.4.5 (#2433)
• Update sbt-scalafix to 0.9.33 (#2431)
• Update sbt-ci-release to 1.5.10 (#2418)
• Update scalacheck-1-14, ... to 3.2.1.0 (#1850)
• Update sbt-ci-release to 1.5.9 (#2364)
• Update scala-parallel-collections to 1.0.4 (#2377)
• Update sbt-mima-plugin to 1.0.1 (#2385)
• Update sbt-protobuf to 0.7.1 (#2378)
• Update sbt-scalafix to 0.9.32 (#2414)
• Update sbt-scalafmt to 2.4.4 (#2417)
• Update commons-text to 1.9 (#1789)
• Update sbt-assembly to 1.1.0 (#1706)
• Update scala-library, scala-reflect to 2.12.15 (#2358)
• Update scala-library, scala-reflect to 2.13.7 (#2401)
• Update sbt-unidoc to 0.5.0 (#2394)
• Update json4s-native to 3.6.12 (#2406)
• Update sbt-scoverage to 1.9.2 (#2402)
• Update antlr4, antlr4-runtime to 4.9.3 (#2407)

Miscellany

• [spec] Fix formatting of example of memory port types. (#2368)
• Have Flatten & InlineInstances remove their annotations (#2374)
• Update spec on extmodule with defname, parameter (#2413)

FIRRTL v1.5.0-RC1

Feature

• Allow Side Effecting Statement to have Names (#2057)
• Stop padding multiply and divide ops (#2058)
• Refactor emitter (#1879)
• Add SortModules Transform (#1905)
• Make {Stage, FirrtlStage}.run protected (#1926)
• Create annotation to allow inline readmem in Verilog (#2107)
• Add -fpga flag to enable FPGA-oriented compilation strategies (currently for memories) (#2111)
• Add NoConstantPropagationAnnotation to disable constant propagation (#2150)
• Add options for memory initialization inside or outside the ifndef SYNTHESIS block. (#2166)
• Add indent parameter to Serializer.serialize() (#2177)
• Rewrite vlsi_mem_gen into a Firrtl Transform, Add GenVerilogMemBehaviorModelAnno & vlsiMemGen (#2202)
• Implement MFC-style source locator compression (#2212)
• Improve performance of RenameMap in LowerTypes (#2233)
• Add -X mhigh compiler for minimal high form (#2268)
• Add Protocol Buffer emission export, this adds infrastructure and annotations that let a user emit a FIRRTL circuit as a Protocol Buffer. (#2271)
• Add a new option to the FIRRTL compiler, "--start-from = ". If used, this will cause the compiler to assume that the input FIRRTL circuit is already in the specific form. It will then skip unnecessary passes given this information. (#2273)
• Relax spec on 0-bit mux select, use SFC behavior, change the FIRRTL specification document to allow for 0-bit mux selects. (#2285)
• Implement NoCommonSubexpressionElimination (#2291)

API Modification

• Memlib Refactor, switch to new API. (#2191)
• Add --dont-fold option to disable folding prim ops (#2040)

Fix

• Fix Serializer for single indented DefModule emission (#2332)
• Bug fix for VerilogPrep using wrong type. (#1932)
• Fix dshl zero-width shift behavior (#2339)
• Fix RemoveWires handling of invalidated non-UInt wires (#1949)
• Fix Type Error fuzzer Example code (#1960)
• Fix subaccess (#1984)
• Remove explicit pom scm from build.sbt (#2004)
• ExpandWhens: ensure that statement names are maintained (#2082)
• Fix ProtoBuf conversions for Verification IR (#2100)
• Fix CSESubAccesses for SubAccesses with flips (#2112)
• Fix cat of zero-width SInt (#2116)
• Fix width of constant propagation of SInt with zero (#2120)
• Fix issue where inlined cvt could cause crash (#2124)
• Legalize neg: -x becomes 0 - x (#2128)
• Ensure InlineCasts does not inline complex Expressions (#2130)
• Fix bug in zero-width memory removal (#2153)
• Don't use declaration-assigns for wires representing mem ports (#2189)
• Fix CheckWidths error message for uninferred width (#2196)
• Fix SBT deprecation warnings (#2214)
• Fix renaming of local targets in InlineInstances (#2238)
• WiringTransform: cannot run after RemoveWires (#2240)
• Fix MultiInfo parser + serialization bug (#2265)
• [spec] Explicit widths may be non-negative, not just positive (#2277)
• Dedup attribute annos, restore annotation order when dedupping annotations (#2297)
• Fix Specification Memory Port Types (#2319)

Miscellany

• Improve performance of LowerTypes renaming (#2024)
• full64 is required to detect VCS. (#1930)
• Remove caching from RenameMap (#1938)
• Fix Type Error fuzzer Example code (#1960)
• Make MultiTargetAnnotation.targets a def (#1969)
• add weak and strong to Utils.v_keywords (#1983)
• Suport ir.SubAccess in Utils.splitRef (#2021)
• IR: turn some IR nodes into data classes (#2071)
• Emit space after 'if' for all Verilog conditional synchronous assignments (#2091)
• don't use protoc-jar anymore, mill can handle it better. (#2162)
• Constant propagation of the Xor op folds xor(a, SInt(0)) toasUInt(a). For comparison, Or folds to asUInt(pad(a, W)). (#2179)
• Make InferTypes error on enable conditions > 1-bit wide (#2182)
• With Stage/Phase, users can provide complex functionality at the phase level rather than just the transform level. It is useful to have the same logging information at that level. Note that this change still logs transforms in the same way (#2190)
• Make MustDeduplicateAnnotation deletable (#2215)
• This function will safely wrap any unserializeable annotations in UnserializeableAnnotations so that they can be safely serialized to JSON for logging. (#2227)
• Replace mem macros renaming (#2243)
• ir: make HashCode.toHashString public. This will allow chiseltest to save the hash code to disk for the purpose of caching simulation binaries. (#2302)
• add emitter for optimized low firrtl (#2304)
• Require Andr, Orr, Xorr, Neg to have one operand (#2312)
• Uses virtual method .getBytesBuffered: Iterable[Array[Byte]] to optimize file emission. (#2334)
• Multiprotobuf algorithm now pulls the top module from the protobufs (#2344)

Verification

• smt: ensure that all signals have a unique name (#1943)
• Fix SMT Memory Bug (#1942)
• smt: add support for write-first memories (#1948)
• smt: add support for uninterpreted ext modules (#1994)
• smt: run DeadCodeElimination after PropagatePresetAnnotations (#2036)
• SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)
• SMT Backend: model Invalid and Division by Zero with DefRandom nodes (#2104)
• SMT: memory port inout fields cannot be used as RHS expressions (#2105)
• smt: use existing bitWidth API(#2175)
• make PresetRegAnnotation public (#2254)
• Replace hard coded line separators with system specific ones (#2281)
• PropagatePresetAnnotations: remove false prerequisites (#2323)(#2325)
• smt make SMTLib + Btor2 emitters public objects, This will make it easier for formal verification libraries to make use of these emitters. (#2326)
• treat stop with non-zero ret like an assertion (#2338)

Testing and Continuous Integration

• Switch from Travis to Github Actions CI (#2041)
• Automatically publish SNAPSHOTs on pushes to master (#1955)
• Restore scalafmt CI check (#2047)
• Fix mill compile and add to CI (#2147)

Documentation

• Fix Mergify badge in README (#1974)
• fix scaladoc for ReferenceTarget (#2014)
• Update spec to disallow 0-bit mux sel (#2305)

Deprecation and Code Removal

• Deprecate ToWorkingIR (#2028)
• Remove Scala 2.11 (#2062)
• Deprecate InlineCasts, add InlineAcrossCasts (#2146)
• Fix RemoveAccesses, delete CSESubAccesses (#2157)
• Deprecate memlib APIs.(#2199)
• Remove java.io in FileUtils, Add deprecation annotation in FileUtils (#2256)
• Deprecate BlackBoxResourceAnno (#2262)
• remove LoweringCompilersSpec, it has outlived its usefulness. (#2310)

Firrtl v1.4.3

Highlights

• Fix performance bug in RemoveAccesses (#2157)
  Normally a bug fix would not be a highlight but this bug has been around for a very long time and could cause quadratic growth in FIRRTL runtime for expanding dynamic indexing of vecs of deeply nested aggregate type.

Feature

• Create annotation to allow inline readmem in Verilog (#2107)
• Add "Must Deduplicate" API (#2077)
• Add NoConstantPropagationAnnotation to disable constatnt propagation (#2150)
  CLI option is --no-constant-propagation
• Add file line to source link in ScalaDoc (#2072)

Bug fixes

• Fix ProtoBuf conversions for Verification IR (#2100)
• Fix cat of zero-width SInt (#2116)
• Fix bug in zero-width memory removal (#2153)
• Legalize neg: -x becomes 0 - x (#2128)
• Ensure InlineCasts does not inline complex Expressions (#2130)
• Fix issue where inlined cvt could cause crash (#2124)
• Fix width of constant propagation of SInt with zero (#2120)
• Fix renaming in verilog prep (#1932)

Firrtl v1.4.2

Highlights

• Improve performance of LowerTypes renaming (bp #2024) (#2025)
• Suport ir.SubAccess in Utils.splitRef (#2021) (#2070)
• Add --dont-fold option to disable folding prim ops (#2040) (#2050)

Bug fixes

• Add newline in the end of LoFIRRTL file (#2015) (#2016)
• fix scaladoc for ReferenceTarget (#2014) (#2020)
• Cleanup some warnings (#2032) (#2051)
• Stop padding multiply and divide ops (#2058) (#2061)

Miscellaneous

• Deprecate ToWorkingIR (#2028) (#2067)
• ConstantPropagation: make RemoveValidIf an optional dependency (#2027) (#2066)
• smt: run DeadCodeElimination after PropagatePresetAnnotations (#2036) (#2043)

Infrastructure

• Fix Mergify badge in README (#1974) (#2010)
• Fix post-merge publishing (#2055) (#2056)
• Bump to Scala 2.12.13 and 2.13.4 (bp #2053) (#2054)
• Restore scalafmt CI check (#2047) (#2049)
• Switch from Travis to Github Actions CI (#2041) (#2044)