asic-design

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …

asic fpga vhdl rtl verilog synthesis fft soc asic-verification asic-design

Updated Dec 3, 2023
Verilog

JeffDeCola / my-verilog-examples

Star

A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated Jul 10, 2023
Verilog

sdnellen / open-register-design-tool

Star

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda verilog systemverilog uvm registers systemrdl register-descriptions systemrdl-compiler fpga-development asic-design

Updated Jan 31, 2024
Verilog

OrsuVenkataKrishnaiah1235 / RTL-Coding

Star

"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

fpga vhdl rtl verilog hdlbits asic-design rtl-design-and-verification rtl-coding hdlbitssolution

Updated Aug 13, 2023
Verilog

mostafa-elgendy22 / PrUcess

Star

PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.

dft verilog synchronizer synthesis formal-verification uart-protocol physical-design asic-design

Updated Apr 29, 2023
Verilog

abdelazeem201 / ORCA

Star

Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology

asic vhdl rtl verilog synthesis synopsys hdl fpga-soc pnr upf asic-design synopsys-vcs synopsys-dc systemonchip synopsys-iccii saed32nm

Updated Sep 10, 2023
Verilog

AhmedAmrAbdellatif1 / Multi-Clock-Domain-System

Star

Design & Implementation of Multi Clock Domain System using Verilog HDL

digital verilog ic-design asic-design

Updated Oct 4, 2023
Verilog

arhamhashmi01 / rv32i-pipeline-processor

Star

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

vhdl verilog microprocessor hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator asic-design chip-design 5-stage-pipelined-processor rv32i-processor

Updated Mar 22, 2024
Verilog

meeeeet / RTL-to-GDS-Implementation-of-SerDes

Star

verilog vlsi-physical-design openroad asic-design rtl2gds

Updated Feb 22, 2024
Verilog

VardhanSuroshi / VLSI-ASIC-Design-Flow

Star

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

opensource rtl vlsi risc-v vlsi-physical-design vlsi-design asic-design skywater openlane

Updated Jan 23, 2024
Verilog

Luca-Dalmasso / LL_contest

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Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT

vhdl tcl synopsys cmos low-power digital-electronics asic-design

Updated Jul 11, 2021
Verilog

Essenceia / Blake2

Star

Blake2 RTL implementation

hashing cryptography asic fpga vhdl rtl verilog blake2b blake2 blake2s fpga-accelerator asic-design

Updated Apr 30, 2023
Verilog

Visruat / VSD-TCL

Star

TCL Script automating the frontend of ASIC design

tcl synthesis static-timing-analysis asic-design

Updated Jun 21, 2023
Verilog

maehw / wokwi-verilog-gds-lowspeed-tiny-uart

Star

300 baud 8N1 UART transmitter with limited character set (0x40..0x5F) loading as ASIC design

uart uart-protocol uart-interface uart-tx uart-transmitter asic-design wokwi tinytapeout

Updated Sep 30, 2022
Verilog

shahed22 / Architectural-Design-for-Bus-interface-connected-with-LFSR

Star

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

asic fsm interface architecture rtl verilog peripherals datapath soc testbench lfsr 32-bit 32bit bus-interface asic-design controlpath datapath-design lfsr-algorithm

Updated May 28, 2024
Verilog

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asic-design

Here are 23 public repositories matching this topic...

dpretet / async_fifo

lirui-shanghaitech / CNN-Accelerator-VLSI

AUCOHL / DFFRAM

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

thousrm / universal_NPU-CNN_accelerator

abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

JeffDeCola / my-verilog-examples

sdnellen / open-register-design-tool

OrsuVenkataKrishnaiah1235 / RTL-Coding

mostafa-elgendy22 / PrUcess

abdelazeem201 / ORCA

AhmedAmrAbdellatif1 / Multi-Clock-Domain-System

arhamhashmi01 / rv32i-pipeline-processor

meeeeet / RTL-to-GDS-Implementation-of-SerDes

VardhanSuroshi / VLSI-ASIC-Design-Flow

Luca-Dalmasso / LL_contest

Essenceia / Blake2

Visruat / VSD-TCL

maehw / wokwi-verilog-gds-lowspeed-tiny-uart

shahed22 / Architectural-Design-for-Bus-interface-connected-with-LFSR

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