VeeR EH1 core
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Updated
May 29, 2023 - SystemVerilog
VeeR EH1 core
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
VeeR EL2 Core
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
Synthesizable SystemVerilog IP-Core of the I2S Receiver
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
BDD Gherkin implementation in native SystemVerilog, based on UVM.
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
Moore.io Demo Project
CPEN 211: Introduction to Microcomputers 2022W1 with Prof. Lis
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