Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
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Updated
Feb 14, 2017 - Verilog
Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
Complete design of a Mini Stereo Digital Audio Processor
An hardware-based text-editor with minimal features and direct VGA output.
FPGA CryptoNight V7 Minner
Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.
A year before the first iPhone launched (2007), I worked on improving the robustness of WiFi chipsets for mobile devices using a data modulation technique called Orthogonal Frequency Division Multiplexing (OFDM). My main focus was developing a low power design for an OFDM core, which would minimize battery drain; thus avoiding the need for bigge…
Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encrypti…
"Low power" digital standard cells for SKY130 provided by SkyWater.
"Medium speed" digital standard cells for SKY130 provided by SkyWater.
"Low speed" digital standard cells for SKY130 provided by SkyWater.
"High voltage" digital standard cells for SKY130 provided by SkyWater.
"High speed" digital standard cells for SKY130 provided by SkyWater.
"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.
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