Chisel: A Modern Hardware Design Language

Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions

An exquisite superscalar RV32GC processor.

Provides dot visualizations of chisel/firrtl circuits

Yet another toy CPU.

educational microarchitectures for risc-v isa

Learning how to make RISC-V 32bit CPU with Chisel

vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

Chisel library for Unum Type-III Posit Arithmetic

Chisel Things for OFDM

Quasar 2.0: Chisel equivalent of SweRV-EL2

A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Tywaves!

An SoC with multiple RISC-V IMA processors.

Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"

BFM Tester for Chisel HDL

Chisel3 AXI4-{Lite, Full, Stream} Definitions

Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, please read the paper that appeared in MICRO 2021 by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

Chisel implementation of Neural Processing Unit for System on the Chip