This is a simple project that shows how to multiply two 8x8 matrixes in Verilog.
-
Updated
May 17, 2024 - Verilog
This is a simple project that shows how to multiply two 8x8 matrixes in Verilog.
verilog model of a 32 bit RISC-V processor core supporting the RV32I instruction set
Contains my resume
Academic Lab Course of the 27th batch of Computer Science & Engineering | University of Rajshahi - 🇧🇩
Smart room management is controlling electronic devices automatically based on the room occupancy. This project is for a maximum of 3 people. It was designed using D flipflops. It was simulated on Logisim.
Descrições em VHDL desenvolvidas durante Sistemas Digitais 1
My activity in digital systems
This code is for the final project of the Digital System Design course taught by Dr.Farshad Baharvand on the Fall semester of 2020
Implementation and verification of a hardware-based controller for a three-phase induction motor on an FPGA — Bachelor's Thesis [UPC-TTU, 2019]
Developed a Fake Currency Detector using Verilog HDL and Implemented the same on a Basys 3 FPGA Board
Verilog implementation of the basic structure of an FPGA
👾 My studies with Verilog and notions of digital systems.
Binary Adder, Subtractor, Multiplier, Divider in VHDL with FPGA board.
Home automation simulation project created for the UofT ECE241 course. Worked on by Harsh Grover and Joonseo Park. More details in README
Implementation of a low-pass FIR filter in Verilog HDL.
Digital Systems Design - Spring 2023 - Sharif University of Technology
Term project and lab assignments for CS303 - Logic and Digital System course in Sabancı University, Fall 2021-2022.
Digital Systems Design With VHDL laboratory sessions, Fall 2018
Add a description, image, and links to the digital-system-design topic page so that developers can more easily learn about it.
To associate your repository with the digital-system-design topic, visit your repo's landing page and select "manage topics."