Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

Automatic generation of real number models from analog circuits

Fast, interactive Julia/GTK+ plots (+Smith charts +Gtk widget +Cairo-only images)

Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

Pure Python async code for talking to the BitScope micro

gnucap mirror (read only)

HSPICE and MATLAB simulation files of a tracking SAR ADC

Code for "Improving Noise Tolerance of Mixed-Signal Neural Networks" https://arxiv.org/abs/1904.01705

Raspberry Pi powered High Altitude Weather Balloon

Open Source PHY v2

Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel

A low noise nanovoltmeter design files and code

A 2 stage CMOS OTA with Differential amplifier with active load as the first stage followed by Common Source stage using Cadence

Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process

This is a novel application of active analog circuits for computing the Cartesian coordinates of points ( targets ) in 2D and 3D space. Two anchors ( points ) are assumed available, with known coordinates. Optical or Infrared Angle-of-Arrival , AOA, (noisy) measurements from each anchor to the uknown target are assumed available.

Some digital circuit simulations done using Logisim (which is an open source logic simulation software package)

Цифров генератор на сигнали с тъчскрийн

A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

A digital function generator which outputs waveforms up to 10 kHz