This course focuses on modern computer system architecture and design principles, with an emphasis on using a Hardware Description Language (HDL) to create fundamental components of a microprocessor’s data path and control unit.

An arcade game implemented in VHDL as an assignment for Digital Systems Analysis & Design course at the University of Guilan, Department of Computer Engineering, presented in Fall 2023 by Dr. Mahdi Aminian.

Laboratorio 1: FPGA. Introducción en el empleo de programación digital en FPGA.

This project template is designed to streamline the development of SystemVerilog projects using Verilator, GTKWave, and Make. The template includes a Makefile with various recipes for compiling, simulating, and visualizing the design. It also includes a directory structure for organizing the HDL files, test benches, and simulation waveforms.

Collection of scripts for EDA tools

Project made in my 1st year at University using Structural VHDL to implement a 4 bit integer multiplier using the MAX DE10-Lite Board

Project made in my 1st Year at University cisisting in combining Hardware in VHDL and Software in Kotlin to recreate the classic SpaceInvaders Game on a MAX DE10 Lite FPGA Board

This repository showcases the projects I developed for the DE10-Lite board as part of the "FPGA Capstone: Building FPGA Projects" course on Coursera.

This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.

An embedded system project of an audio player made using Altera Max 10 FPGA, Quartus Prime & NIOS II

This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book. The project includes a complete Verilog implementation, supporting various instruction types, with performance enhancements and detailed schematics for analysis.

Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.

PERIDOT Standard peripherals

A script to convert the Intel Quartus IDE to dark mode using QDarkStyleSheet with some modifications.

Team 21 - Mini-Project

Utilised System Verilog to create the 74LS93 Counter

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs

A Tiny RISC Calculator implemented on the DE-10 Lite using Quartus Prime