Open-source high-performance RISC-V processor

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions

An exquisite superscalar RV32GC processor.

A RISC-V Core (RV32I) written in Chisel HDL

Yet another toy CPU.

Learning how to make RISC-V 32bit CPU with Chisel

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

A fault-injection framework using Chisel and FIRRTL

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.

An out-of-order processor that supports multiple instruction sets.

Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"

Network components (NIC, Switch) for FireBox

『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ

BOOM's Simulation Accelerator.

This is my graduation project, a simple processor soft core, which implements RV32I ISA.

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

mini risc-v kernel by Chisel 3