risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 136 public repositories matching this topic...
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
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Jan 4, 2024 - Assembly
Functional verification project for the CORE-V family of RISC-V cores.
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May 14, 2024 - Assembly
RISC-V Zve32x Vector Coprocessor
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Dec 2, 2023 - Assembly
Fast constant-time AES implementations on 32-bit architectures
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Nov 30, 2022 - Assembly
32-bit RISC-V Forth for microcontrollers
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May 29, 2023 - Assembly
Bare-metal Forth implementation for RISC-V
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Feb 9, 2024 - Assembly
high performance AES implementations optimized for cortex-m microcontrollers
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May 12, 2024 - Assembly
A baremetal experiment of Allwinner D1, without FEL
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May 4, 2023 - Assembly
Materials for the "Computer Architecture and Operating Systems" course taught at Faculty of Computer Science of Higher School of Economics
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Apr 21, 2024 - Assembly
Assembly Guide
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Jan 2, 2022 - Assembly
RISC-V Assembly code assembler package for Python.
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Mar 31, 2024 - Assembly
An instruction set simulator (ISS) for the RV32/64I subset of the RISC-V instruction set.
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Nov 5, 2020 - Assembly
some exercises written in Assembly RISC-V @ Sapienza 2020
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Aug 28, 2021 - Assembly