🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A simple RISC-V processor for use in FPGA designs.

Basic RISC-V CPU implementation in VHDL.

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

IEEE 754 floating point library in system-verilog and vhdl

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

IEEE 754 floating point library in system-verilog and vhdl

VexRiscV system with GDB-Server in Hardware

A simple three-stage RISC-V CPU

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

16 bit RISC-V proof of concept

RISC V 32 bit Base ISA Implementation.

HARV - HArdened Risc-V

Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture

Simple RISC-V RV32I CPU in VHDL for use in FPGA Designs

Trabalho de Organização e Arquitetura de Computadores, UnB - 2020/2

Neuromorphic architectures are hardware architectures that use the biologically inspired neural functions as the basis of operation. Information processing based on spiking neuron architectures have caught considerable attention in recent years due to its low power consumption compared to traditional artificial neural networks. In this project, …

Arilla - a RISC-V based microcomputer system, with a PS2 mouse controller and 12-bit RGB SVGA graphics card, running Arilla Paint.

RISC-V based microprocessor system for Altera DE0 FPGA board

A small RISC-V core (VHDL)