risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 94 public repositories matching this topic...
VeeR EH1 core
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May 29, 2023 - SystemVerilog
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
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May 25, 2024 - SystemVerilog
VeeR EL2 Core
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May 29, 2024 - SystemVerilog
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
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Nov 14, 2018 - SystemVerilog
Arquivos base para o projeto da disciplina Infraestrutura de Hardware (IF674) no CIn-UFPE.
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Mar 19, 2024 - SystemVerilog
Vector processor for RISC-V vector ISA
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Oct 19, 2020 - SystemVerilog
Advanced Architecture Labs with CVA6
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Jan 16, 2024 - SystemVerilog
Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
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May 30, 2024 - SystemVerilog
Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
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Mar 13, 2024 - SystemVerilog