riscv32
Here are 20 public repositories matching this topic...
A pipelined, in-order implementation of the RV32I ISA
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Aug 9, 2020 - SystemVerilog
Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.
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Oct 8, 2020 - SystemVerilog
DUTH RISC-V Microprocessor
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Mar 10, 2021 - SystemVerilog
Undergraduate level RISC-V microcontroller
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Oct 12, 2022 - SystemVerilog
A Single Cycle Risc-V 32 bit CPU
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Feb 11, 2023 - SystemVerilog
An attempt at making a customised RISC processor with five pipelined stages and supporting all RISC-V instruction set
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May 13, 2023 - SystemVerilog
VeeR EH1 core
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May 29, 2023 - SystemVerilog
RISCV core RV32I/E.4 threads in a ring architecture
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Jun 12, 2023 - SystemVerilog
Implementing a 32-bit processor using RISC-V architecture.
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Dec 23, 2023 - SystemVerilog
RISC-V processor co-simulation using SystemVerilog HDL and UVM.
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Jan 15, 2024 - SystemVerilog
Creating a risc-v processor
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Apr 4, 2024 - SystemVerilog
Implementación del procesador monociclo RISC-V en System Verilog.
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May 6, 2024 - SystemVerilog
grape is a single cycle RISC-V [RV32I] processor synthesised using SystemVerilog. This project was done as a part of the RISC-V Architecture course(UE20EC302). This my first attempt in building a processor.
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May 12, 2024 - SystemVerilog
VeeR EL2 Core
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May 27, 2024 - SystemVerilog
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