RISC-V
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Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 61 public repositories matching this topic...
CRYPTOGAMS distribution repository
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Jun 3, 2024 - Assembly
A collection of exercises in Assembly Language done following the RISCV protocol
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Apr 17, 2024 - Assembly
A stack-based language implemented in RISC-V assembly
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Apr 4, 2024 - Assembly
RISC-V Assembly code assembler package for Python.
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Mar 31, 2024 - Assembly
This simple lines of code could test the bit manipulation instructions.
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Mar 12, 2024 - Assembly
Demo of a prototype using MLLite for training and deployment of Machine Learning Models on various devices and microcontrollers.
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Feb 20, 2024 - Assembly
My Bachelor's Thesis "Optimizing Ascon for 32-bit Architectures, Fast Implementations for RISC-V and Xtensa"
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Feb 15, 2024 - Assembly
Architectural Tests for RISC-V Steel Processor Core IP
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Feb 4, 2024 - Assembly
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
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Jan 4, 2024 - Assembly