rtl
Here are 48 public repositories matching this topic...
VeeR EL2 Core
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May 28, 2024 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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May 27, 2024 - SystemVerilog
This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.
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May 22, 2024 - SystemVerilog
Test suite designed to check compliance with the SystemVerilog standard.
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May 20, 2024 - SystemVerilog
learning about FPGA
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May 20, 2024 - SystemVerilog
Common SystemVerilog RTL modules for RgGen
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May 15, 2024 - SystemVerilog
BDD Gherkin implementation in native SystemVerilog, based on UVM.
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Apr 27, 2024 - SystemVerilog
This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language
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Apr 11, 2024 - SystemVerilog
Pequeno aka pqr5 is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I
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Apr 6, 2024 - SystemVerilog
Creating a risc-v processor
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Apr 4, 2024 - SystemVerilog
Syntacore scr1 iALU verification example
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Mar 7, 2024 - SystemVerilog
Developing RISC-V CPU
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Jan 29, 2024 - SystemVerilog
Library containing various VHDL IPs
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Jan 5, 2024 - SystemVerilog
SPI-Master Controller example + peripheral devices simulation
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Dec 12, 2023 - SystemVerilog
This repository contains different modules which execute arithmetic operations.
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Sep 23, 2023 - SystemVerilog
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