Overview: The goal of this project is to design an SDRAM controller that allows SDRAM memory to be interfaced with a microprocessor having only asynchronous memory support. There is no requirement to build the hardware, but a complete written report containing schematics and theory of operation is required

High-Speed SystemVerilog SDRAM Controller

🛠 A SDRAM controller in Verilog HDL

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

SDR SDRAM Controller with Avalon-MM bus; [Bugged, deprecated]

SDRAM controller

Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.

A HDL SDRAM controller designed for retro hardware and FPGAs

Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

SDRAM Tester implemented in FPGA

Verilog HDL implementation of SDRAM controller and SDRAM model

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

Simple SDRAM Controller for DE10-Lite.

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

SDRAM controller optimized to a memory bandwidth of 316MB/s

SDRAM controller with AXI4 interface

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。