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Jun 3, 2024 - VHDL
systemverilog
Here are 34 public repositories matching this topic...
Implementation of a particle detector using a cheap FPGA developement board. The FPGA exploits some ADCs and then if there are coincidences in the signals, the event is recorded.
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Apr 12, 2024 - VHDL
Python Frontend For VHDL And Verilog
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Mar 26, 2024 - VHDL
Trying to verify Verilog/VHDL designs with formal methods and tools
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Mar 7, 2024 - VHDL
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
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Dec 6, 2023 - VHDL
Every Day I will be uploading an RTL code with Synthesized Design and TB for RISC CPU Design
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Dec 4, 2023 - VHDL
Este repositório foi criado para armazenar códigos feitos durante o andamento da cadeira de Circuitos lógicos II do curso de Engenharia de Computação da UFPB. Todos os códigos foram desenvolvidos utilizando system verilog.
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Nov 7, 2023 - VHDL
Kuantek University Program
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Oct 12, 2023 - VHDL
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May 17, 2023 - VHDL
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
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May 6, 2023 - VHDL
ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.
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Feb 14, 2023 - VHDL
A fully automated testbench for microcontroller CPU CISC
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Sep 23, 2022 - VHDL
Hardware acceleration of edge detection algorithm
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Sep 15, 2022 - VHDL
This is my implementation of a Sampler using the ARTY A7 35T developement board by Digilent.
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Apr 15, 2022 - VHDL
simple demo hardware code for implement access to ST7789 LCD display from FPGA
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Mar 28, 2022 - VHDL
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