verilog-code

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Here are 98 public repositories matching this topic...

CutlerCasey / school_bs_ce

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Code done while obtaining my Bachelor of Science in Computer Engineering. Java was not my expertise in College.

python c java cpp cuda verilog verilog-code

Updated Jan 15, 2019
Java

ntuifranklin / ENES-246

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fpga verilog vivado digital-logic digital-logic-design digital-logic-simplification verilog-code

Updated Mar 4, 2019
JavaScript

mihir8181 / VerilogHDL-Codes

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Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

counter fsm asynchronous verilog fifo testbenches verilog-hdl verilog-programs mealy-machine-code moore-machine-code verilog-project fifo-buffer verilog-code n-bit-alu verilogvalidation design-under-test asynchronous-fifo fifo-verilog

Updated May 10, 2019
Verilog

benitoss / UnAmiga

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Implementation of Amiga 500/1200 in Altera Cyclone IV FPGA

verilog-code

Updated Jun 4, 2019
VHDL

mongrelgem / UART-RTL-Physical-Design

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Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2

layout verilog uart hardware-designs uart-interface verilog-code

Updated Sep 3, 2019
Perl

p4r4xor / verilog-labs

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Pin-point analysis of the questions given in labs using FPGA and ASIC design.

verilog verilog-programs verilog-code

Updated Nov 13, 2019

Sanskar777 / QRS-peak-detection-in-ECG-signals-using-verilog

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ecg-signal ecg-qrs-detection verilog-code curve-length-transform qrs-peak-detection

Updated Dec 1, 2019
Verilog

jayaramanrp / system-verilog

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simple system verilog files

constraints systemverilog verilog-code

Updated Jan 22, 2020
SystemVerilog

kazutomo / Chisel-DE1SOC-FPGA-template

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A template Chisel project for the DE1SOC FPGA board

scala fpga chisel quartus verilog-code

Updated Feb 13, 2020
Scala

aditeyabaral / DDCO-Lab-UE18CS207

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A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

verilog logic-programming icarus-verilog digital-design computer-organization verilog-code

Updated Apr 17, 2020
Verilog

djzenma / RV32IC-CPU

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Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

cpu verilog risc hdl pipeline-processor verilog-hdl risc-v rv32i verilog-snippets pipeline-cpu risc-processor riscv32 riscv-simulator rv32imc verilog-code riscv32im

Updated May 29, 2020
Verilog

franklinthony / food-machine

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Projeto de uma máquina de lanche desenvolvido como atividade final da disciplina Circuitos Lógicos II.

academic-project verilog-project verilog-code food-machine

Updated Jul 10, 2020
Verilog

Arjun-Narula / Traffic-Light-Controller-using-Verilog

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the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

Updated Jul 18, 2020
JavaScript

ARohithReddy / multiplier

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Digital circuit description to perform multiplication with data_path and control_path using verilog

verilog datapath multiplier data-path verilog-code controlpath

Updated Jul 30, 2020
Verilog

trojanink / University-projects

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Some of the projects I developed during my studies at University of Thessaly, Electrical & Computer Engineering Dpt.

c university assembly homework projects verilog assembly-language assembly-language-programming studies c-language verilog-components verilog-project verilog-code c-language-math computer-engineering-dpt

Updated Aug 6, 2020
C

GirloftheLimberlost / DigitalLockFPGA

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FPGA Digital Lock System with 7 Segment LED Display - Password changeable (Hexadecimal Passwords)

fpga verilog led seven-segments-display verilog-project verilog-code

Updated Aug 14, 2020

zeeshan0309 / pseudo_random_sequence_generator

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systemverilog lfsr pseudo-random pseudo-random-generator verilog-code

Updated Aug 22, 2020
SystemVerilog

pankajpatro703 / hdlang-ex

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Hardware Description Language(HDL) based codes using Verilog & VHDL for reference.

hdl vhdl-code verilog-code

Updated Sep 15, 2020
Verilog

MSaaad / vlsi-lab-tasks

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Codes performed in labs using Xilinx ISE 14.7

verilog vlsi-design verilog-code

Updated Sep 15, 2020
Verilog

PXVI / std_module

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All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.

encoder decoder rtl mux fifo adder lfsr shifter subtractor verilog-code siso verilog-modules

Updated Oct 20, 2020
Verilog

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verilog-code

Here are 98 public repositories matching this topic...

CutlerCasey / school_bs_ce

ntuifranklin / ENES-246

mihir8181 / VerilogHDL-Codes

benitoss / UnAmiga

mongrelgem / UART-RTL-Physical-Design

p4r4xor / verilog-labs

Sanskar777 / QRS-peak-detection-in-ECG-signals-using-verilog

jayaramanrp / system-verilog

kazutomo / Chisel-DE1SOC-FPGA-template

aditeyabaral / DDCO-Lab-UE18CS207

djzenma / RV32IC-CPU

franklinthony / food-machine

Arjun-Narula / Traffic-Light-Controller-using-Verilog

ARohithReddy / multiplier

trojanink / University-projects

GirloftheLimberlost / DigitalLockFPGA

zeeshan0309 / pseudo_random_sequence_generator

pankajpatro703 / hdlang-ex

MSaaad / vlsi-lab-tasks

PXVI / std_module

Improve this page

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