vhdl
Here are 110 public repositories matching this topic...
A flexible and scalable development platform for modern FPGA projects.
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Jul 9, 2024 - Python
Configurable AES-GCM IP (128, 192, 256 bits)
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Jul 8, 2024 - Python
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
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Jul 8, 2024 - Python
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
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Jul 7, 2024 - Python
Trying to build a risc v cpu using logisim, trying is the key idea here.
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Jul 6, 2024 - Python
An abstract language model of VHDL written in Python.
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Jul 5, 2024 - Python
A toolbox for automating some of the more tedious refactoring tasks comming with common HDL languages (VHDL/Verilog). Including among others: entity to instance conversion and entity cross language conversion.
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Jun 30, 2024 - Python
Gather version information and export as any programming language source file for inclusion into compilation.
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Jul 5, 2024 - Python
An abstraction library for interfacing EDA tools
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Jul 8, 2024 - Python
A simple python script to generate a VHDL testbench template given an entity-architecture declaration passed as argument(s) as a file(s)
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Jun 28, 2024 - Python
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
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Jun 22, 2024 - Python
Cross EDA Abstraction and Automation
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Jul 4, 2024 - Python
A functional verification framework for digital hardware.
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Jun 20, 2024 - Python
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