learning about FPGA
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Updated
May 20, 2024 - SystemVerilog
learning about FPGA
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.
4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.
This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language
Notes after working with Zynq platform using vivado and petalinux
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
Developing RISC-V CPU
Library containing various VHDL IPs
8-bit multiplier module implemented on SystemVerilog meant for the xc7s50csga324-1 Spartan 7 FPGA
A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.
running ANN on an FPGA
NESystem Verilog
Logic Analyzer IP Core
This repository contains the Xilinx Vivado project for the Artix-7 (XC7A35T-1FTG256C) FPGA on Virtex.
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
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