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Logic Analyzer IP Core
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Jul 23, 2022 - SystemVerilog
Library containing various VHDL IPs
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Jan 5, 2024 - SystemVerilog
learning about FPGA
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May 20, 2024 - SystemVerilog
Notes after working with Zynq platform using vivado and petalinux
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Feb 26, 2024 - SystemVerilog
FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol
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Dec 2, 2021 - SystemVerilog
8-bit multiplier module implemented on SystemVerilog meant for the xc7s50csga324-1 Spartan 7 FPGA
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Sep 23, 2023 - SystemVerilog
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
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Feb 16, 2024 - SystemVerilog
An cellular automata game for a 8x8 matrix on the BetiBoard. (requires Basys3 board)
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Mar 20, 2020 - SystemVerilog
Stress test power subsystem of your Xilinx FPGA board
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Apr 8, 2018 - SystemVerilog
An FPGA implementation of Cummings' Asynchronous FIFO
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Apr 14, 2022 - SystemVerilog
Undergraduate level RISC-V microcontroller
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Oct 12, 2022 - SystemVerilog
All projects that utilize the Verilog & SystemVerilog HDL's.
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Aug 23, 2022 - SystemVerilog
Hardware-side component of Hastlayer for Xilinx Vitis FPGAs. See https://hastlayer.com for details.
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Jan 29, 2024 - SystemVerilog
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