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NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
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Jul 7, 2020 - SystemVerilog
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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Nov 25, 2019 - SystemVerilog
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
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Apr 8, 2024 - SystemVerilog
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
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Feb 9, 2022 - SystemVerilog
Logic Analyzer IP Core
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Jul 23, 2022 - SystemVerilog
Library containing various VHDL IPs
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Jan 5, 2024 - SystemVerilog
FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol
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Dec 2, 2021 - SystemVerilog
Stress test power subsystem of your Xilinx FPGA board
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Apr 8, 2018 - SystemVerilog
An FPGA implementation of Cummings' Asynchronous FIFO
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Apr 14, 2022 - SystemVerilog
All projects that utilize the Verilog & SystemVerilog HDL's.
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Aug 23, 2022 - SystemVerilog
Hardware-side component of Hastlayer for Xilinx Vitis FPGAs. See https://hastlayer.com for details.
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Jan 29, 2024 - SystemVerilog
Notes after working with Zynq platform using vivado and petalinux
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Feb 26, 2024 - SystemVerilog
An cellular automata game for a 8x8 matrix on the BetiBoard. (requires Basys3 board)
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Mar 20, 2020 - SystemVerilog
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