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Must-have verilog systemverilog modules
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Jun 27, 2024 - Verilog
HITSZ 2024 数字电路技术实验 FPGA Verilog 代码仓库
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Jun 13, 2024 - Verilog
This is a simple project that shows how to multiply two 8x8 matrixes in Verilog.
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May 17, 2024 - Verilog
Plugins for Yosys developed as part of the F4PGA project.
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May 14, 2024 - Verilog
This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.
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Apr 27, 2024 - Verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
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Mar 15, 2024 - Verilog
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
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Feb 27, 2024 - Verilog
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
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Feb 25, 2024 - Verilog
Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
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Jan 26, 2024 - Verilog
Dual-Mode PSK Transceiver on SDR With FPGA
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Jan 17, 2024 - Verilog
A bare-metal SRAM memory controller suitable for Xilinx FPGAs.
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Jan 15, 2024 - Verilog
Bus bridges and other odds and ends
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Jan 12, 2024 - Verilog
This project aims to design a hardware encryption and decryption scheme for the Data Encryption Standard (DES) algorithm
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Jan 6, 2024 - Verilog
3rd Order Moving Average(FIR) Filter Implementation On FPGA.
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Nov 10, 2023 - Verilog
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