AD463x Platform FPGA Architecture
The AD463x digital host consists of DSP (digital signal processor), or an FPGA (Field Programmable Gate Array). In this case we use the Intel Cyclone V SoC FPGA with a dual core ARM Cortex A9 hard processor system (HPS) with the embedded Analog Devices .
The Intel Cyclone V SoC FPGA serves as the digital host for the AD463x ADCs. It also implements various interfaces and modules for configuration, control, status, dma, as well as conversion data processing and host processing. Additionally, there are external data/control and video peripheral interfaces implemented in the FPGA for use on the DataStorm DAQ.
The AD4630-24 is a two-channel, simultaneous sampling, Easy Drive, 2 MSPS successive approximation register (SAR) analog-to digital converter (ADC). For details, consult the datasheet and its operation on the EVAL-AD4630-24FMCZ evaluation board.
The toplevel ports for the fpga are as follows:
Name | Direction | Description |
---|---|---|
sys_clk | input | main clock |
ddr3_a[15:0] | output | HPS DDR3 Address bus |
ddr3_ba[2:0] | output | HPS DDR3 Bank Address |
ddr3_reset_n | output | HPS DDR3 active low Reset |
ddr3_ck_p | output | HPS DDR3 Differential clock positive rail |
ddr3_ck_n | output | HPS DDR3 Differential clock negative rail |
ddr3_cke | output | HPS DDR3 clock enable |
ddr3_cs_n | output | HPS DDR3 active-low chip select |
ddr3_ras_n | output | HPS DDR3 active-low row address strobe |
ddr3_cas_n | output | HPS DDR3 active-low column address strobe |
ddr3_we_n | output | HPS DDR3 active-low write enable |
ddr3_dq[31:0] | inout | HPS DDR3 32-bit bidirectional data bus |
ddr3_dqs_p[3:0] | inout | HPS DDR3 4-bit bidir differential data strobe positive rail |
ddr3_dqs_n[3:0] | inout | HPS DDR3 4-bit bidir differential data strobe negative rail |
ddr3_dm[3:0] | inout | HPS DDR3 4-bit bidir data mask |
ddr3_odt | output | HPS DDR3 on-die termination |
ddr3_rzq | output | HPS DDR3 output drive calibration (to RZQ resistor) |
eth1_tx_clk | output | HPS ethernet mac transmit interface clock |
eth1_tx_ctl | output | HPS ethernet mac transmit interface control |
eth1_tx_d[3:0] | output | HPS ethernet mac transmit interface 4-bit data bus |
eth1_rx_clk | input | HPS ethernet mac receive interface clock |
eth1_rx_ctl | input | HPS ethernet mac receive interface control |
eth1_rx_d[3:0] | input | HPS ethernet mac receive interface 4-bit data bus |
eth1_mdc | output | HPS ethernet mac management data i/o interface clock |
eth1_mdio | inout | HPS ethernet mac management data input/output |
link_st | inout | HPS ethernet mac link state |
rx_er | inout | HPS ethernet mac receive error |
phy_int | inout | HPS ethernet PHY interrupt |
eth_rst | inout | HPS ethernet reset |
phy_led1 | inout | HPS ethernet PHY led 1 |
qspi_ss0 | output | HPS Quad SPI chip select 0 |
qspi_clk | output | HPS Quad SPI clock out |
qspi_io[3:0] | inout | HPS Quad SPI data 3 to 0 |
sdio_clk | output | HPS SDIO Clock |
sdio_cmd | inout | HPS SDIO command |
sdio_d[3:0] | inout | HPS SDIO bidir data |
usb1_clk | input | HPS USB interface clock |
usb1_stp | output | HPS USB interface STOP signal |
usb1_dir | input | HPS USB interface Direction |
usb1_nxt | input | HPS USB interface Next |
usb1_d[3:0] | inout | HPS USB interface 8-bit bidir data |
usb1_rst | inout | HPS USB interface reset |
uart0_rx | input | HPS UART0 RX data |
uart0_tx | output | HPS UART0 TX data |
hps_scl | inout | HPS I2C interface serial clock |
hps_sda | inout | HPS I2C interface serial data |
hdmi_clk | output | HDMI Clock |
hdmi_de | output | HDMI Data enable |
hdmi_hsync | output | HDMI Horizontal Sync |
hdmi_vsync | output | HDMI Vertical Sync |
hdmi_data[23:0] | output | HDMI Data |
hdmi_spdif | output | HDMI Sony/Philips Digital Interface |
hdmi_spdifout | input | HDMI Sony/Philips Digital Interface out |
hmdi_int | input | HMDI int |
ct_hpd | output | |
ls_oe | output | |
cec_clk | output | Consumer Electronics Control Clk |
fmc_scl | inout | FMC I2C clock |
fcm sda | inout | FMC I2C data |
ad463x_cnv | output | ADC start of conversion signal for AD463x ADC |
ad463x_csn | output | Active-low SPI chip select |
ad463x_sclk | output | SPI Clock to AD463x ADC |
ad463x_sdo | output | SPI data out to AD463x ADC |
ad463x_sdi | input | SPI data in 8lanes from AD463x ADC |
ad463x_echo | input | echo clock input from AD463x ADC |
ad463x_busy | input | multiplexed busy and master clock input from AD463x ADC |
fmc_pg_c2m | inout | |
fmc_prsnt_m2c | inout | |
cpu_gpio_0 | inout | |
cpu_gpio_1 | inout | |
led_hps_1 | inout | |
led_hps_2 | inout | |
therm_n | inout | |
alert_n | inout | |
user_btn_hps | inout | |
status | inout | |
as_rst | inout | |
qspi_rst | inout |
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