AD7768 Platform FPGA Architecture spi_interface

SPI Controller

A 3-wire Serial Peripheral Interface (SPI) controller implemented as a peripheral to the HPS (hard proessor system) in the Intel Cyclone V SoC FPGA, used for reading/writing the register map in AD7768 when in spi-control mode.

The AD7768 has a 4-wire SPI interface that operates in SPI Mode 0, which makes it compatible with the HPS SPI implementation. In SPI Mode 0, SCLK idles low, the falling edge of CSE clocks out the MSB, the falling edge of SCLK is the drive edge, and the rising edge of SCLK is the sample edge. This means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge.

The SPI serial control interface of the AD7768 is an independent path for controlling and monitoring the AD7768. There is no direct link to the data interface. SPI access is ignored during the period immediately after a reset. Allow the full ADC start-up time after resetto elapse before accessing the AD7768/AD7768-4 over the SPI interface.

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