Datastorm DAQ GHRD create hps

Create the Processor System using Platform Designer

• Open Platform Designer from Quartus Prime via one of the two methods below:

  • Tools -> Platform Designer menu, or
  • Click on its icon in the tool bar.  A blank project is created with a default name of unsaved.qsys.

• Do a File -> Save As … to give it the name system_bd.qsys. This saves the file in the project folder .../partial_source/.

• When Saving is done, click Close.

Add peripheral modules from the IP Catalog

Add the HPS IP (Hard Processor System IP)

Either type HPS in the IP Catalog search bar or, expand the Processors and Peripherals -> Hard Processor Systems and double-click Arria V/Cyclone V Hard Processor System to add it to the system.

This action opens the HPS configuration window.

• In the FPGA Interfaces tab,
  • un-check all boxes.
  • Leave the AXI Bridges set to their defaults.
  • In the FPGA-to-HPS SDRAM Interface section:
    • Change f2h_sdram0 type to be Avalon-MM Bidirectional and keep it 64-bit.
    • Use the + to add 2 more interfaces: f2h_sdram1 and f2h_sdram2 as type AXI-3 64-bit.
• In the Interrupts section, check the box to Enable FPGA-to-HPS interrupts.

• Select the Peripheral Pins tab and set the peripheral pins as follows:

  Controller	Pin	Setting	Mode	Setting
  Ethernet Media Access Controller	EMAC1 pin	HPS I/O Set 0	EMAC1 mode	RGMII
  Quad SPI Flash Controller	QSPI pin	HPS I/O Set 0	QSPI mode	1SS
  SD/MMC Controller	SDIO pin	HPS I/O Set 0	SDIO mode	4-bit Data
  USB Controller	USB1 pin	HPS I/O Set 0	USB1 PHY interface mode	SDR with PHY clock output mode
  UART Controller	UART0 pin	HPS I/O Set 0	UART0 mode	No Flow Control
  I2C Controller	I2C0 pin	HPS I/O Set 1	I2C1 pin	HPS I/O Set 0

• Scroll down to the bottom of the Peripheral Pins window until the Peripheral Mux Table is visible.
• Scroll the table to the right until the GPIO column is visible and click the following pins:
  • GPIO00
  • GPIO09
  • GPIO35
  • GPIO40-44
  • GPIO48
  • GPIO53-59
  • GPIO61
  • GPIO65

• Select the HPS Clocks tab and keep all settings in the Input Clocks sub-tab at defaults.

• Select the Output Clocks sub-tab and change the following selections from their defaults:
  • In the Main PLL Output Clocks section, change the Configuration/HPS-to-FPGA user 0 clock frequency to 80.0 MHz
  • In the HPS-to-FPGA User Clocks section, check only the box for Enable HPS-to-FPGA user 1 clock

• Select the SDRAM tab.
  • In the PHY Settings sub-tab, set:
    • Memory clock frequency to 333.3 MHz
    • PLL reference clock frequency to 25MHz

• Select the Memory Parameters sub-tab and set the following:

  Parameter	Setting
  Memory device speed grade	800.0 MHz
  Total interface width	32 (which will automatically update the Number of DQS groups to 4)
  Row address width	15
  Column address width	10
  Memory CAS latency setting	5
  ODT Rtt nominal value	RZQ/6
  Memory write CAS latency setting	5

• Select the Memory Timing sub-tab and set the values as shown in the figure below:

• Select the Board Settings sub-tab.
  • In the Board Skews section change the setting to match the figure below:

• Click Finish in the bottom right corner of the window.

In the System Contents tab do the following:

• Rename the clk_0 module to sys_clk by right-clicking the name -> Rename,

• Rename the hps_0 module to sys_hps,

• Double-click in the memory row Export column and call it sys_hps_memory,

• Double-click in the hps_io row Export column and call it sys_hps_hps_io,

• Double-click in the h2f_reset row Export column and call it sys_hps_h2f_reset,

• Under sys_clk row, double-click the Export column in clk_in row and rename it sys_clk,

• Still under sys_clk, double-click in Export column in clk_in_reset row and rename it sys_rst,

• Form signal connections.
  Note: For this and future steps, all signals with possible connection paths are shown with light grey line segments. Each possible connection point is shown as an empty bubble at the vertex of the line segments. Form a connection by clicking on this bubble and then the line turns dark black to show the completed connection. Hover the mouse over the vertex to see the names of the signals of the connection.

  • Now connect the sys_hps_h2f_user1_clock to the following signals under the Hard Processor System sys_hps:
    • f2h_sdram0_clock
    • f2h_sdram1_clock
    • f2h_sdram2_clock
    • h2f_axi_clock
    • f2h_axi_clock
    • h2f_lw_axi_clock

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